Self-* Systems CSE 598B

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Self- SystemsCSE 598B

• Paper title Dynamic ECC tuning for caches
• Presented by Niranjan Soundararajan

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Abstract

• On-chip caches are increasing in sizes
• Protection needed in order to store correct data.
• ECC serves as an efficient means to protect the
  data
• ECC has its own overhead
• Area Extra space for its logic
• Latency ECC computations take time
• This work deals with reducing latency involved in
  ECC computation.
• Track the cache lines frequently accessed.
• Dynamically turn ECC computation on and off for
  specific cache lines.

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Background

• Information redundancy
• Data in the processing core is protected by
  schemes such as RMT (Redundant Multi-threading)
  12.
• ECC protection is easy to implement for on-chip
  caches. Also size of the caches prevent them from
  being replicated 3.
• Current evaluation shows raw FIT (Failures In
  Time) rate numbers for latches and SRAM cells to
  vary between 0.001 0.01 FIT/bit. This value
  increases with elevation. At 1.5 km FIT/bit is
  3.5x while at 10 km (airplanes) FIT/bit is 100x
  larger 4567.

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Background

• As processor power dissipation becomes more and
  more important, supply voltages get reduced. This
  will greatly increase the FIT/bit 89.
• As an example, consider a 32 MB data cache. This
  cache has 222 quad-words. Let us assume that an
  SRAM cell has an average FIT rate of 0.001. The
  single-bit FIT rate for the entire cache is 0.001
  222 72 3.02 105,i.e. the MTTF is 109 /
  (3.02 105) 3311 hours 3.
• Consider the case of large multiprocessor systems
  with tens of megabytes of caches. Protection
  becomes an important issue if the systems are
  involved in critical computations like space
  research and flight control.

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Background

• All these data point out that cache data must be
  protected. ECC is the best way to protect SRAM.
• This work addresses some of the problems related
  to applying ECC for caches that need to operate
  at low latency like the L1 caches.

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Motivation

• ECC overhead 10
• Increase in area due to circuitry 11 (approx.
  15mm2)
• Increase in latency 10 (approx 5 ns)
• Applications show temporal locality in accessing
  cache lines. By dynamically turning ECC on and
  off for cache lines, latency of cache access gets
  reduced. Since the frequency of operations is
  going to be high, the time between individual
  accesses is going to be less.

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Motivation

• Chance of error affecting data is less
• Due to frequency of operations
• Cache lines with high temporal locality is less
  compared to total number of cache lines.

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Benchmarks
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Benchmarks
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Benchmarks
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Self-Tuning Implementation

• Keep track of cache line access. After every 5000
  cycles, tune the ECC of cache lines to turn on or
  off.
• Overhead
• Keeping track of cache line access Simple, fast
  counters make implementation easy.
• Tuning ECC for lines Simple average computation
  and turning ECC on for lines with more activity
  than the average.

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Implementation

• Implementation simplified if
• Counters maintained for a set of cache lines.
• ECC tuning done at this granularity.
• Granularity can be at 10, 20 100 lines.

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Self-tuning Results

• From the graphs we see the temporal locality.
  Based on these results, ECC was turned off for
  the lines with high locality.

BENCHMARK RELATIVE ACCESS FREQUENCY OVERHEAD
WUPWISE 8.3 0.5
VPR-ROUTE 5.9 2.5
PARSER 11.9 2.7
PERLBMK 6.3 2.5
GCC 2.7 1.9
GZIP 4.7 3.2
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Conclusion

• ECC is indispensable as chip reliability reduces
  and maintaining correct data becomes an issue.
• Processor-Memory bottleneck is an eternal issue.
  Increasing cache latency through ECC protection
  creates further problems.
• This work tries to reduce cache (protected by
  ECC) latency using a scheme to dynamically turn
  ECC on and off.

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