5x5 Pixel Array Status 17 Dec 2003 - PowerPoint PPT Presentation

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5x5 Pixel Array Status 17 Dec 2003

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Title: 25 Element Pixel Array Author: S Burke Last modified by: sburke Created Date: 12/1/2002 8:10:59 PM Category: ASIC Project Document presentation format – PowerPoint PPT presentation

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Title: 5x5 Pixel Array Status 17 Dec 2003


1
5x5 Pixel Array Status17 Dec 2003
Sam Burke Sean Stromberg UCSB HEP Group
2
ASIC Progress
  • AMI CMOS 0.35 Design Kit 2 Received
  • Design Manual C035MD Ver 5
  • Design Manual C035MA Ver 3
  • Core Cells, D Scan FFs, LVDS Library
  • Pad Limited and Core Limited I/O Cells
  • Ver 1.8 Databook, Ver1.0 Technology Info

3
Transmission Gate
  • The Trans-Gate will be one of the building
    blocks for the D FlipFlop along with inverters.
  • V Rs
  • 0 volts 2100 ohms
  • 1 3000
  • 2 4500
  • 3 6500
  • Load Resistor will be needed if float causes
    voltage decay lag problem

4
Transmission Gate
  • Pulse Response
  • Cload .08pf
  • Rload1meg
  • Tplh330ps

5
Work Plan
  • Characterize AMI035 min-size transistors
  • transfer curves characteristic curves size
  • Generate desired parameters for inverter
  • Td h/l Td l/h Vsw-Td with 1-Inv load
  • Td with 4-Inv loads Match h/l and l/h Tds?
  • Simulate Ring Oscillator with inverter
  • determine Td or Fmax
  • Define desired D Flip Flop with Clear

6
DFFR
  • D Flip Flop with Reset
  • 4 inverters
  • 4 transmission-gates
  • 2 2-input NAND
  • 24 separate FETs in design!
  • Active low reset

7
DFFR Simulation Goals
  • Ts Setup time gt 0.13ns
  • Th Hold time gt 0.11ns
  • Tclk-min Minumum clock pulse width gt 0.20ns
  • Trec Recovery time gt .06ns
  • Fclk-max Max Clock Freq lt 950 Mhz
  • Td Delay time lt 0.53 ns
  • Size 50 x 12 u (600 u2)
  • Reference times based AMI035 FD2SS specs (AMI
    std-cell design data book)

8
DFFR Spice Results
9
DFFR Spice Results
10
DFFR Spice Net List
11
DFFR Simulation
  • Critical D Flip Flop time delays are compared to
    those stated for the AMI FD2SS D Flip Flop
  • Using L0.35u, W0.8u which is the minimum size
    transistor. If W2 3W1 then high-low and
    low-high transitions will be equal and clocking
    rate will increase, see analysis which follows.
  • Delay Time Td
  • AMI Std Cell DFFR Simulation
  • lt0.53 ns 5.2 ns ?
  • Max Clock Frequency Fclk-max
  • 950 Mhz 96 Mhz

12
Ring Oscillator
  • Inverters have W2W1 which results in unequal
    propigation delays.
  • Tphl 0.9 ns
  • Tplh1.3 ns

13
Ring Oscillator Revised
  • W23W1 for near equal prop delays
  • Tphl732ps
  • Tplh589ps
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