Methods for checking simulation correctness

1

• Methods for checking simulation correctness

How do you know if your testcase passed or failed?
2

• 3 checking methods

• Predict and check
• Check as you go
• Trace and check later

3

• Predict and check

• How does it work?
• Create the stimulus
• Run the stimulus against an independent reference
  model
• Save the predicted results
• Run the stimulus on the simulation model
• Compare the simulation results against the
  predicted results
• Where is it used?
• Processor verification
• Chip verification

4

• Predict and check - cont'd

... m 00000100 830445cd6673da21 m 00000108
34539877c7c82243 m 00000110 cd565479802ad999 ... i
ld r4, (100) i ld r8, (110) i add r4,
r8, r3 i add r3, r4, r8 i add r3, r3,
r8 ... m 00000100 830445cd98098001 m 00000108
34539877c7c82243 ...
5

• Predict and check - cont'd

Disadvantages
Advantages

• Does not require run time interaction with the
  model
• Reference model tends to be highly reusable
• Quickly up and running and producing bugs

• Bugs must propagate to a result
• Bugs can be overwritten
• Cascade affect can make it difficult to isolate
  the source of the problem
• Results have to be predictable from the testcase
  alone
• Input may have to be restricted to guarantee
  predictable results

6

• Check as you go

• How does it work?
• Create an environment to stimulate, observe and
  predict the behavior of the simulation model
• As the simulation is running the environment
  should compare the expected behavior to the
  observed behavior
• Stop the testcase when the expected and observed
  behavior is different
• Where is it used?
• unit verification
• chip verification
• subsystem verification

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Check as you go - cont'd

• DUV

(IM Interface Monitor)
8

• Check as you go - cont'd

Advantages
Disadvantages

• Highly effective at finding all types of bugs
• Stops the test as soon as the error is detected
• Error messages can be very specific and are
  usually directly related to the problem
• Environment can choose what to do next based upon
  observed events

• Environment code is greater than the VHDL
• Environment may be created to match the
  implementation instead of the design intent
• Takes time to make the environment effective
• Requires run time iteraction with the model
• Code is very design specific and not reusable

9

• Trace and check later

• How does it work?
• Tracers are created to observe and record the
  activity of specific interfaces
• During the simulation of the testcase the trace
  information is gathered and saved
• After the simulation is complete, the tracers are
  analyzed for any rule violations
• Where is it used?
• system verification
• protocol verification

10

• Trace and check later - cont'd

11

• Trace and check later - cont'd

Disadvantages
Advantages

• Don't spend simulation time checking results
• Stimulus generation is not constrained
• Allows correlation between distant parts of the
  design under verification
• Tracers and checkers reusable for standard
  interfaces

• Bugs must propagate to an observed interface to
  be seen
• Testcase will run to completion before any error
  checking is started (wasted cycles)
• Requires run time interaction with the model

12
Data Response Timeout
P4
P5

• P1

P3
P6
P2
Respond Shared
Read addr 100
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