ECE%20601%20-%20Digital%20System%20Design%20

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ECE 551 Digital System Design Synthesis
Lecture Set 4 4.1 Verilog Procedural
Assignments Scheduling
Semantics 4.2 Verilog
More Behavioral
Descriptions
(In separate file)
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ECE 601 - Digital System Design Synthesis
Lecture 4.1 Procedural Assignments
Scheduling Semantics

• Overview
• Blocking Non-Blocking Assignments
• The Verilog Stratified Event Queue
• Determinism and Non-determinism
• Guaranteed ordering
• Ambiguous ordering
• Blocking Non-Blocking Assignments with Delays
• Interacting Behaviors
• Coding Guidelines

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Procedural Assignments in General

• Assignment consists of two parts
• Evaluation of the right hand side (RHS)
• Assignment of evaluation to left hand side (LHS)
• Delays can affect
• Time of execution of the current and subsequent
  assignments,
• Time of evaluation of the RHS
• Time of assignment to the LHS
• Type of assignment (blocking, non-blocking) can
  affect the times as well

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Blocking Assignments

• Identified by
• Sequence of blocking assignments executes
  sequentially
• An assignment must be completed before the next
  assignment is activated for consideration.
• Inter-assignment delays block both evaluation and
  update
• Intra-assignment delays block update but not
  evaluation

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Nonblocking Assignments

• Identified by lt
• Nonblocking assignments without delays execute
  simultaneously
• An assignment need not complete for consideration
  of subsequent assignments for execution.
• Inter-assignment delays block both evaluation and
  update as well as consideration of subsequent
  assignments
• Intra-assignment delays block update but do not
  block evaluation or consideration of subsequence
  assignments for evaluation
• Nonblocking assignments for a given behavior are
  scheduled last.

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Blocking Non-Blocking Assignments Examples - 1

• Non-Blocking
• reg70 A, B, C, D
• always_at_(posedge clk)
• begin
• A lt B C
• B lt A D
• C lt A B
• end

• Blocking
• reg70 A, B, C, D
• always_at_(posedge clk)
• begin
• A B C
• B A D
• C A B
• end

• initial begin
• A 8h1 B 8h2 C 8h3 D 8h4 end

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Blocking Non-blocking Assignment Examples - 2

• Simulation
• Results

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Simulation of Simultaneous Assignments

• Scheduling semantics need to be defined for
  simulation
• For consistency of simulation results and
  synthesized hardware behavior, these semantics
  need to be mimicked by synthesis tools
• Scheduling semantics defined by
• Verilog Stratified Event Queue

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Event Simulation Terminology 2

• Update event every change in value of a net or
  register. Also a named event.
• Processes execute in response to update events in
  arbitrary order.
• Evaluation event the evaluation of a process.
• Simulation time is the time value used by the
  simulator to model actual time.
• Events are kept in an event queue.
• Scheduling an event putting an event on a queue.

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The Verilog Stratified Event Queue - 1

• Five Regions
• Region 1 Active Events events that occur at
  the current simulation time and can be processed
  on any order.
• Region 2 Inactive Events - events that occur at
  the current simulation time, but that shall be
  processed after all active events.
• Region 3 Non-blocking Assign Update Events
  Events that have been evaluated at some previous
  simulation time, but shall be assigned at this
  simulation time after all active and inactive
  events are processed.

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The Verilog Stratified Event Queue - 2

• Five Regions (Continued)
• Region 4 Monitor Events Events that shall be
  processed after all active, inactive, and
  nonblocking assign update events.
• Region 5 Future Events Events that occur at
  some future simulation time. Include future
  inactive events and future nonblocking assignment
  events.

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More Terminology 2

• Simulation cycle the processing of all active
  events.
• Explicit zero delay (0) forces the process to
  be suspended and added as inactive event for the
  next simulation cycle.
• Non-blocking assignment creates a nonblocking
  assign update event at the current or a later
  simulation time.
• monitor and strobe system tasks create monitor
  events for their arguments
• Re-enabled in every successive time step
• Monitor events cannot create any other events
• Certain PLI (Programming Language Interface)
  procedures are treated as inactive events.

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Verilog Sim Reference Model - 1

• T is current simulation time and all events are
  held in event queue, ordered by simulation time
• While (there are events)
• if (no active events)
• if (there are inactive events)
• activate all inactive events
• else if (there are nonblocking assign update
  events)
• activate all nonblocking update events
• else if (there are monitor events)
• activate all monitor events
• else advance T to the next event time
• activate all inactive events for
  time T

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Verilog Simulation Reference Model - 2

• E any active event
• if (E is an update event)
• update the modified object
• add evaluation events for sensitive processes
  to the event queue
• else /shall be an evaluation event /
• evaluate the process
• add update events to the event queue

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Determinism 2

• Standard guarantees a certain scheduling order
• Statements within a begin-end block shall be
  executed in the order in which they appear
  although the processing can be suspended in favor
  of other processes in the model.
• Nonblocking assignments shall be performed in the
  order the statements are executed, i. e., they
  are queued, taken from the queue and performed in
  the order of the statements.

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Nondeterminism 2

• Active events that be taken from the queue and
  processed in any order
• Statements without time-control constructs (,_at_)
  in behavioral blocks do not have to be executed
  as one event.
• The simulator may suspend execution and place the
  partially-completed event as a pending active
  event on the event queue.
• The ordering of this interleaving of execution is
  nondeterministic and not under user control.

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Scheduling Implications of Assignments (Partial)

• Continuous assignment when value of expression
  changes schedules update event
• Procedural continuous assignment similar to
  continuous assignment
• Blocking assignment (intra-assignment delay)
  computes RHS, then causes process to be suspended
  and scheduled as a future event. When process
  returns, assigns LHS and enable events based on
  update of LHS.
• Nonblocking assignment computes updated value
  and schedules update as a nonblocking assign
  update event in current or future time step.

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Blocking Assignment Example Inter-assignment
Delay

• Delays both the evaluation and the update
• Example always _at_(posedge clk)
• begin
• b a a
• 5 c b a
• 2 d c a
• end
• initial begin a 3 b 2 c 1 end
• What are the results for b, c and d and when do
  they occur?

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Blocking Assignment Example - Intra-Assignment
Delay

• Delays the update, but not the evaluation
• Example always _at_(posedge clk)
• begin
• b a a
• c 5 b a
• d 2 c a
• end
• initial begin a 3 b 2 c 1 end
• What are the results for b, c and d, and when do
  they occur?

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Non-Blocking Assignment Example
Inter-assignment Delay

• Delays both the evaluation and the update
• Example always _at_(posedge clk)
• begin
• b lt a a
• 5 c lt b a
• 2 d lt c a
• end
• initial begin a 3 b 2 c 1 end
• What are the results for b, c and d and when do
  they occur?

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Non-Blocking Assignment - Intra-Assignment Delay

• Delays the update, but not the evaluation
• Example always _at_(posedge clk)
• begin
• b a a
• c 5 b a
• d 2 c a
• end
• initial begin a 3 b 2 c 1 end
• What are the results for b, c and d, and when do
  they occur?

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Assignments with Delays Simulation Results
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Mixed Blocking/Nonblocking Assignment Example

• Example always _at_(posedge clk)
• begin
• b a a
• c lt b a
• 2 d lt c a
• c d a
• end
• Initial begin a 3 b 2 c 1 d 0 end
• Example What are the results for b, c, and d,
  and when do they occur?

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Mixed Blocking/Non-blocking Simulation Results
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Interacting Behaviors - 1

• Example
• always _at_ (posedge clk)
• begin
• A lt B
• end

always _at_ (A or C) begin D C end

• Non-blocking assignment execution causes
  blocking assignment execution to follow it in
  same timestep.

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Interacting Behaviors - 2

• Example (from Cummings 1)
• always _at_ (posedge clk or posedge rst)
• if (rst) y1 0 //reset
• else y1 y2
• always _at_ (posedge clk or posedge rst)
• if (rst) y2 1 // preset
• else y2 y1
• If first always first after reset, y1 y2 1.
  If second always first after reset, y2 y1 0.
• Thus results are order dependent and ambiguous, a
  Verilog race condition.

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Interacting Behaviors - 3

• Example (from Cummings 1)
• always _at_ (posedge clk or posedge rst)
• if (rst) y1 lt 0 //reset
• else y1 lt y2
• always _at_ (posedge clk or posedge rst)
• if (rst) y2 lt 1 // preset
• else y2 lt y1
• Regardless of which always executes first, by the
  Verilog standard, the assignments for y1 and y2
  occur in parallel at the end of the timestep,
  giving y1 1 and y2 0.
• Thus results are order-independent.

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Coding Guidelines 1

• 1 When modeling sequential logic, use
  nonblocking assignments.
• 2 When modeling latches, use nonblocking
  assignments. (flip-flops?)
• 3 When modeling combinational logic with an
  always block, use blocking assignments.
• 4 When modeling both sequential and
  combinational logic within the same always block,
  use nonblocking assignments.

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Coding Guidelines 1(Continued)

• 5 Do not mix blocking and nonblocking
  assignments in the same always block.
• 6 Do not make assignments to the same variable
  from more than one always block.
• 7 Use strobe to display values that have been
  assigned using nonblocking assignments.
• 8 Do not make assignments using 0 delays.

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Coding Guidelines Comments on Cummings 3

• Verilogs event queue can be rerun in the same
  timestep if non-blocking events trigger always
  statements (CRK can cause nonblocking statements
  not to be last in timestep).
• Blocking assignments with delays, one per
  separate always statement is a viable alternative
  (CRK But for synthesis? Seems like a bad idea.)
• You can safely mix blocking assignments
  (combinational logic) and nonblocking assignments
  (flip-flops) in the same edge-triggered always
  statement, provided the nonblocking statements
  are last in the always (although may cause
  problems with false latch generation in
  synthesis).

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References

• 1. Cummings, Clifford E., Nonblocking
  Assignments in Verilog Synthesis, Coding Styles
  That Kill!, SNUG-2000.
• 2. IEEE, IEEE Standard Hardware Description
  Language Based on the Verilog Hardware
  Description Language, IEEE Std 1364-1995.
• Campbell, Paul, A note on Verilog assignments,
  Verifarm, Inc., http//www.verifarm.com/assign.sht
  ml