Variability-Driven Formulation for Simultaneous Gate Sizing and Post-Silicon Tunability Allocation

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Variability-Driven Formulation for Simultaneous
Gate Sizing and Post-Silicon Tunability Allocation
Natalia Vinnik University of California, Los
Angeles Based on presentation and paper by
Vishal Khandelwal and Ankur Srivastava Department
of Electrical and Computer Engineering,University
of Maryland College Park http//www.ece.umd.edu/v
ishalk
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Outline

• Introduction
• Process variation traditional gate sizing
• Post-Silicon Tunable (PST) Clock Tree Buffers
• Optimization objective
• Problem statement
• Two-stage formulation
• Experimental results
• Summary and Future Work

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Introduction

• Process variations cause significant spread in
  design performance in sub 90nm technologies
• Impact yield and reliability
• It is necessary to explicitly consider the impact
  of process variations on design parameters
• Several statistical analysis and optimization
  techniques have been proposed to improve
  timing/power yields

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Handling Process Variations
Process Variations
Design-Time Optimization
Post-Fabrication Tunability

• Statistical Gate Sizing
• Statistical Buffer Insertion

• Post-Silicon Tunable Clock-Tree Buffers

Davoodi, DAC06 Sapatnekar, DAC05 Zhou,
ICCAD05
Chen, ICCAD05 Mahoney, ISSC05 Takahashi,
2003 Tam, JSSC00
He, ISPD06 Davoodi, ICCD05 Wong,
ICCAD05 Khandelwal, ICCAD03
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Traditional Gate Sizing

• Gate size si
• Minimize area, or power
• Subject to
• meeting a delay constraint at the output
• size constraints

Fishburn, Dunlop 1985 Sapatnekar,1993
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Traditional Gate Sizing
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Effects of Process Variations
Set of random variables with arbitrary
distributions

• Delay of each gate becomes a random variable
• Statistical Gate Sizing

Davoodi, DAC06 Sapatnekar, DAC05 Zhou,
ICCAD05
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Post-Silicon Tunable (PST) Clock Tree Buffers

• Tunable clock buffers can introduce extra slack
  into critical paths after fabrication
• Design Overhead
• Area, Clock-Tree Power

Chen, ICCAD05 Mahoney, ISSC05 Takahashi,
2003 Tam, JSSC00
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Post-Silicon Tunable Clock Tree Buffers

• Let Dij be the delay of the longest path between
  flip-flops i and j
• Consider Flip-Flops 2 and 7 Tune buffers to
  change clock-skew

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Optimization Objective Tunability Cost

• Metric to capture the overhead due to PST buffers
  in the design
• Silicon Area
• Clock-Tree Power

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Problem Statement

• Given a sequential design with a synthesized PST
  clock-tree (known buffer locations), perform
  simultaneous
• Statistical gate sizing
• PST buffer tuning range determination
• Such that Binning Yield Loss and Tunability Cost
  is minimized

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Mathematical Analysis of this problem

Tcons
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Two-Stage Formulation

• Gate Size , Tuning Buffer Range

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Second Stage Formulation

• No Statistical Timing Analysis scheme exists to
  estimate the timing distribution of a circuit
  given gate sizes and tuning buffer ranges
• Each sample of variability requires different
  amount of tuning for maximum timing yield

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Convex Problem
THEOREM The proposed two-stage stochastic
programming formulation is convex PROOF Detaile
d proof omitted for brevity

• First stage constraints are convex
• First stage objective is convex if BYL(x,r) is
  convex
• From second stage formulation one can show that
• is convex

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Shortest-Path Constraints

• Inherently non-convex in nature
• Approximate gate delay using a linear
  approximation (lower bound)
• The two-stage stochastic programming formulation
  can be modified to consider shortest path
  constraints

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Experimental Results

• Experimental Comparison ISCAS benchmarks
• Chen
• Nominal gate sizing
• PST clock-tree generation using Chen et. al,
  ICCAD05
• Sensitivity
• Retain PST clock-tree location and range
• Sensitivity-driven statistical gate sizing
  algorithm
• Size the gate with maximum yield gain greedily
  (iterative)
• Similar in spirit to Zhou ICCAD05, Zolotov
  DAC05
• Stochastic
• Retain PST clock-tree buffer locations
• Proposed simultaneous gate sizing and
  post-silicon tunability allocation algorithm

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BYL, Area and Tuning Range Comparison
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Timing Yield Loss Comparison
Chen Sensitivity Stochastic
Average Timing Yield Loss 0.22 0.19 0.03
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Runtime Comparison
Technique s344 s382 s400 s526 s635
Sensitivity 24 40 18 15 109
Stochastic 7 19 13 14 7
Number of Iterations
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Summary and Future Work

• Variability-driven framework for simultaneous
  gate sizing and post-silicon tunability
  allocation to minimize binning-yield loss and
  tunability cost
• Efficient stochastic programming based scheme to
  solve the formulation
• No assumptions about parameter distribution or
  their correlations
• Need to develop a statistical timing analysis
  scheme that can consider the effect of
  post-silicon tunability

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Thank You!