CMOS INVERTER

1
CMOS INVERTER
2
DIGITAL GATES Fundamental Parameters

• Functionality
• Reliability, Robustness
• Area
• Performance
• Speed (delay)
• Power Consumption
• Energy

3
The Ideal Gate
4
VTC of Real Inverter
5
The CMOS Inverter A First Glance
6
CMOS Properties

• Full rail-to-rail swing
• Symmetrical VTC
• Propagation delay function of load capacitance
  and resistance of transistors
• No static power dissipation
• Direct path current during switching

7
Voltage TransferCharacteristic
8
PMOS Load Lines
9
CMOS Inverter Load Characteristics
V
4
in
V
3
V
2
in
in
1
V
4
in
V
2
V
3
in
in
in
V
5
in
10
CMOS Inverter VTC
11
Simulated VTC
12
Gate Switching Threshold
13
Impact of process variations
14
VIH, VIL and gain
15
Propagation Delay
16
Computing CMOS inverter delay in the quadratic
model
V
out
V
DD
Vdd - VTN
t
17
Computing CMOS inverter delay in the linear model
V
DD
t
f(R
.C
)
pHL
on
L
0.69 R
C
on
L
V
out
V
ln(0.5)
out
C
L
V
1
R
DD
on
0.5
0.36
V
V
in
DD
t
R
C
on
L
18
NMOS/PMOS ratio
19
Impact of Rise Time on Delay
20
Delay as a function of VDD
21
Power Consumption
22
Where Does Power Go in CMOS?

• Dynamic Power Consumption
• Charging and Discharging Capacitors
• Short Circuit Currents
• Short Circuit Path between Supply Rails during
  Switching
• Leakage
• Leaking diodes and transistors

23
Dynamic Power Dissipation
2
Energy/transition C
V
L
dd
2
Power Energy/transition
f
C
V

f
L
dd
Not a function of transistor sizes!
Need to reduce C
, V
, and
f
to reduce power.
L
dd
24
Short circuit current
25
Minimizing SC Power
Keep the input and output fall time the same
26
Leakage (static) power
Sub-threshold current is one of the
most Compelling issues in low-energy design
27
Reverse-biased diode leakage

• JSJSA
• JS1-5pA/µm2 in 1.2µm CMOS
• JS doubles with every 90C in T

28
Sub-threshold leakage