TITLE : types of BIST

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TITLE types of BIST
UNIT 5 Built-in Self Test
MODULE 5.1 BIST basics
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Content of BIST architectures

• BIST architectures consist of several key
  elements
• TPG Test pattern generator
• ORA Output response Analyzer
• CUT circuit under test
• DIST Distribution system for transmitting data
  from TPGs to CUTs and from CUTs to ORAs
• BISTC BIST controller for controlling the BIST
  circuitry and CUT during self-test.

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BIST controller

• BIST controller carry out the following
  functions
• Single-step the CUTs through some output test
  sequence.
• Inhibit system clocks and control test clocks.
• Communicate with other test controllers, possibly
  using test busses.
• Control the operation of a self-test.

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BIST Techniques

• The BIST techniques are classified based on the
  operational condition of the circuit under test
  (CUT)
• Off-Line BIST
• On-Line BIST

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On-Line BIST

• Testing occures during normal functional
  operating conditions (No test mode, Real-Time
  error detection).
• Concurrent Occures simultaneously with normal
  functional operation (Realized by using coding
  techniques).
• Nonconcurrent Carried out while in idle state
  (Interruptible in any state, realized by
  executing diagnostic software/firmware routines).

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Off-Line BIST

• Deals with testing a system when it is not
  carrying out its normal functions (Test mode,
  Non-Real-Time error detection).
• Testing by using either on-board TPG Output
  Response Analyzer (ORA) or Microdiagnostic
  routines.
• Structural Execution based on the structure of
  the CUT(Explicit fault model - LFSR, ...).
• Functional Running based on functional
  description of CUT(Functional fault model -
  Diagnostic software).

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TYPES of BIST architecture
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4 types of BIST architectures

• Taking the combination of types in which BIST
  architecture can be divided we get 4 types of
  BIST architecture
• Separate and Centralized BIST
• Separate and Distributed BIST
• Embedded and Centralized BIST
• Embedded and Distributed BIST.

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Distributed and Seperate

• Distributed BIST
• Each CUT is associated with its own TPG and ORA
  circuitry.
• This leads to more overhead but less time.
• This provide more accurate diagnosis.

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Centralized and embedded

• Centralized BIST
• Centralized BIST architecture share several CUTs
  share TPG and ORA circuitry.
• This lead to reduce overhead but increased test
  time.

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Centralized and Separate

• Separate BIST architecture
• TPG and ORA is external to the CUT, not part of
  functional circuitry.

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Embedded and Distributed

• Embedded BIST
• TPG and ORA elements are configured from
  functional elements within the CUT, such as
  registers.
• More complex design, but it has less hardware.

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Choice of a BIST architecture depends on

• Degree of test parallelism
• Fault coverage
• Level of packaging
• Test time
• Physical constraints
• Complexity of replaceable units
• Factory and field test-and-repair strategy
• Performance degradation