ALU Implementation On XC 4010E/XL FPGA Using VHDL

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ALU Implementation OnXC 4010E/XL FPGAUsing VHDL
by Aman Sareen School of Electrical Engineering
and Computer Science Ohio University
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Inputs and Outputs of ALU

• Inputs
• A gt 8 bit word
• B gt 8 bit word
• MODE
• CI
• OPCOCE gt 4 bit word

• Outputs
• Z gt 8 bit word
• COUT
• OVF

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ALU Operations
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Experimental Layout
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ALU SIMULATOR
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Layout on FPGADevice UtilizationTiming
Analysis
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Complete Picture of whats there in the chip
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Circuit Only
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(No Transcript)
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(No Transcript)
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Device Utilization Summary
Number of CLBs 212 out of 400 Flops/latches 80
4 input LUTs 385 3 input LUTs 65 Number of
BUFGLSs 3 out of 8 Number of oscillators 1
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Device Utilization by percentage
IOB 35/160 21 used CLB 212/400 53
used BUFGLS 3/8 37 used OSCILLATOR 1/1 100
used
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Timing Analysis
Average Connection Delay for this design
is 6.057 ns Average Connection Delay on critical
nets is 0.000 ns Average Clock Skew for this
design is 0.118 ns Maximum Pin Delay
is 24.316 ns Average Connection Delay on the
10 Worst Nets is 20.040 ns
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Simulation Results
MODE 0, CI 0 A00111001 B11100011
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Simulation Results
MODE 1, CI 0 A00111001 B11100011
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Simulation Results
MODE 1, CI 1 A00111001 B11100011