Annie

1
Annies Central CardStatus Report -
8/21/2015The University of Chicago
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ACC SpecsGeneral
LED
QSFP
VME P1
RJ45
8 x RJ45
or
5V
16 x RJ45
6U VME32 or VME 64x Format Can work as Stand
Alone
VME P2
Ethernet
SMA
USB
5 x SMA
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ACC SpecsSystem
LED
QSFP
VME P1
RJ45
8 x RJ45
or

• LVDS System Interface
• RJ45 with
• LVDS Clock in
• 2 x LVDS In
• 1 x LVDS Out

5V
16 x RJ45
VME P2
Ethernet
SMA
USB
5 x SMA
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Annie System Interface and Clock Distribution
LVDS IN
RJ45
112
LVDS IN
System Clock IN
LVDS OUT
Local Clock
To FPGA

• Note
• Clocks to FE do not come from the FPGA
• Clocks to FE are fixed, not from PLL.
• Clocks to FE are routed to equal length
  (/-2.5mm)

To FE 8 x clocks
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ACC SpecsFront End
LED
QSFP
VME P1
RJ45
8 x RJ45
or
LVDS Front End Interface Each FE Unit serviced
via 2xRJ45 ACC can service 4 or 8 FE Units.
5V
16 x RJ45
VME P2
Ethernet
SMA
USB
5 x SMA
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ACC SpecsFront End Interface
LVDS In/Out lines within one FE group are length
matched to /-5mm. (Clock Out line not included
here)
LVDS Out
LVDS Out
Clock Out
LVDS In
FE
LVDS In
LVDS In
LVDS In
LVDS Out
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Annie CrateArchitecture
Annie Crate Master (ACM) Same module Different
Firmware
ACC-0

• Double Width ACM
• One ACM Card can service 8 ACCs. System can be
  extended in multiples of 8, in a pyramid scheme.
• Single Width ACM
• One ACM Card can service 4 ACCs. System can be
  extended in multiples of 4, in a pyramid scheme.
• New ACM can be designed to service up to 16 ACCs.

ACC-3

ACC-7
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ACC - situation and plans

• Questions/To Do List
• Finalize Specifications
• Finalize Schematic, Layout
• http//edg.uchicago.edu/bogdan/AnniesCentralCard/
  index.html
• Finalize Top Level FPGA Design
• Start work on functional FPGA Design.