Chapter 1 Introduction to VLSI Design

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Chapter 1Introduction to VLSI Design
Lecture 11 High Desecration Language-Based
Design
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HDL-Based Design
1980s Hardware Description Languages (HDL) were
conceived to facilitate the information exchange
between design groups.
1990s The increasing computation power led to
the introduction of logic synthesizers that can
translate the description in HDL into a
synthesized gate-level net-list of the design.
2000s Modern synthesis algorithms can optimize
a digital design and explore different
alternatives to identify the design that best
meets the requirements.
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Modeling Digital Systems

• VHDL is for writing models of a system
• Reasons for modeling
• requirements specification
• documentation
• testing using simulation
• formal verification
• synthesis
• Goal
• most reliable design process, with minimum cost
  and time
• avoid design errors!

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HDL-Based Design
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Verilog

• Other than VHDL there are many hardware
  description languages available in the market for
  the digital designers such as Verilog, ABEL,
  PALASM, CUPL, and etc
• VHDL and Verilog are the most widely used HDLs.
• The major difference between hardware description
  programming languages and others is the
  integration of time.
• Timing specifications are used to incorporate
  propagation delays present in the system.

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Types of Representation

• VHDL representation can be seen as text file
  describing a digital system. The digital system
  can be represented in different forms such as a
  behavioral model or a structural model. Most
  commonly known as levels of abstraction, these
  levels help the designer to develop complex
  systems efficiently.

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VHDL Programming Structure

• Entity and Architecture are the two main basic
  programming structures in VHDL.
• Entity Entity can be seen as the black box view
  of the system. We define the inputs and outputs
  of the system which we need to interface.
• Entity ANDGATE is
• Port (A in std_logic
• B in std_logic
• Y out std_logic)
• End entity ANDGATE
• Architecture Architecture defines what is in our
  black box that we described using ENTITY. We can
  use either behavioral or structural models to
  describe our system in the architecture. In
  Architecture we will have interconnections,
  processes, components, etc.

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• Architecture AND1 of ANDGATE is
• --declarations
• Begin
• --statements
• Y lt A AND B
• End architecture AND1
• Example
• entity andgate is
• port (A,Bin std_logic
• Cout std_logic)
• end andgate
• architecture b of andgate is
• begin
• --and is a basic VHDL operation. lt represents
  the signal assignment
• CltA and B
• end b

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Basic VHDL Concepts

• Interfaces
• Behavior
• Structure
• Test Benches
• Analysis, elaboration, simulation
• Synthesis

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Modeling Interfaces

• Entity declaration
• describes the input/output ports of a module

entity name
port names
port mode (direction)
entity reg4 is port ( d0, d1, d2, d3, en, clk
in bit q0, q1, q2, q3 out bit )end
entity reg4
punctuation
port type
reserved words
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VHDL-87

• Omit entity at end of entity declaration

entity reg4 is port ( d0, d1, d2, d3, en, clk
in bit q0, q1, q2, q3 out bit )end reg4
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Modeling Behavior

• Architecture body
• describes an implementation of an entity
• may be several per entity
• Behavioral architecture
• describes the algorithm performed by the module
• contains
• process statements, each containing
• sequential statements, including
• signal assignment statements and
• wait statements

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Modeling Behavior
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Modeling Structure

• Structural architecture
• implements the module as a composition of
  subsystems
• contains
• signal declarations, for internal
  interconnections
• the entity ports are also treated as signals
• component instances
• instances of previously declared
  entity/architecture pairs
• port maps in component instances
• connect signals to component ports
• wait statements

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VHDL-87

• Cant directly instantiate entity/architecture
  pair
• Instead
• include component declarations in structural
  architecture body
• templates for entity declarations
• instantiate components
• write a configuration declaration
• binds entity/architecture pair to each
  instantiated component

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