Semiconductor Device Modeling and Characterization EE5342, Lecture 20 -Sp 2002 PowerPoint PPT Presentation

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Title: Semiconductor Device Modeling and Characterization EE5342, Lecture 20 -Sp 2002


1
Semiconductor Device Modeling and
CharacterizationEE5342, Lecture 20 -Sp 2002
  • Professor Ronald L. Carter
  • ronc_at_uta.edu
  • http//www.uta.edu/ronc/

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Equivalent circuitabove OSI
  • Depl depth given by the maximum depl xd,max
    2eSi2fp/(qNa)1/2
  • Depl cap, Cd,min eSi/xd,max
  • Oxide cap, COx eOx/xOx
  • Net C is the series comb

COx
Cd,min
3
MOS surface statesp- substr n-channel
4
n-substr accumulation (p-channel)
Fig 10.7a
5
n-substrate depletion(p-channel)
Fig 10.7b
6
n-substrate inversion(p-channel)
Fig 10.7
7
Ideal 2-terminalMOS capacitor/diode
VgateVG
conducting gate, area LW
-xox
SiO2
0
y
0
L
silicon substrate
tsub
VsubVB
x
8
Band models (approx. scale)
metal
silicon dioxide
p-type s/c
Eo
Eo
qcox 0.95 eV
Eo
qcSi 4.0eV
qfm 4.28 eV for Al
Ec
qfs,p
Eg,ox 8 eV
Ec
EFm
EFi
EFp
Ev
Ev
9
Flat band with oxidecharge (approx. scale)
Al
SiO2
p-Si
lt--Vox--gt-
q(Vox)
Ec,Ox
q(ffp-cox)
Ex
q(fm-cox)
Eg,ox8eV
Ec
EFm
EFi
EFp
q(VFB)
Ev
VFB VG-VB, when Si bands are flat
Ev
10
Values for gate workfunction, fm
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Values for fmswith metal gate
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Values for fmswith silicon gate
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Experimental valuesfor fms
Fig 10.15
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Calculation of thethreshold cond, VT
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Equations forVT calculation
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Fully biased n-MOScapacitor
VG
Channel if VG gt VT
VS
VD
EOx,xgt 0
e- e- e- e- e- e-
n
n
p-substrate
VsubVB
Acceptors
Depl Reg
y
0
L
17
Effect of contacts,VS and VD
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Computing theD.R. width at O.S.I.
Ex
Emax
x
19
Computing thethreshold voltage
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Fully biased MOScapacitor in inversion
VGgtVT
Channel
VSVC
VDVC
EOx,xgt 0
e- e- e- e- e- e-
n
n
p-substrate
VsubVB
Acceptors
Depl Reg
y
0
L
24
Flat band with oxidecharge (approx. scale)
Al
SiO2
p-Si
lt--Vox--gt-
q(Vox)
Ec,Ox
q(ffp-cox)
Ex
q(fm-cox)
Eg,ox8eV
Ec
EFm
EFi
EFp
q(VFB)
Ev
VFB VG-VB, when Si bands are flat
Ev
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Flat-band parametersfor n-channel (p-subst)
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MOS energy bands atSi surface for n-channel
Fig 8.10
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Fully biased n-channel VT calc
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References
Semiconductor Physics Devices, by Donald A.
Neamen, Irwin, Chicago, 1997. Device
Electronics for Integrated Circuits, 2nd ed., by
Richard S. Muller and Theodore I. Kamins, John
Wiley and Sons, New York, 1986
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