ECE-L304 Lecture 5

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ECE-L304 Lecture 5
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Step 3 LabComplete
LED Array
Resistor Array
Self-Clocked ADC
DAC
8-pin header Data Bus Test Port
Timing Filter Components
External Components
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Step 4

• Purpose
• Introduce the static RAM chip
• Write mode, read mode
• Introduce the address generator
• Step the address from 00H to FFH (256 steps)
  using 8 bits
• H indicates hexadecimal format
• Introduce control
• Record 256 words in RAM, then play back

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This Week

• Step 4 Prelab
• Skim the data sheet for the 1 MB RAM chip
• Look for control and timing information
• Step 4 Lab
• Simulate a simple data acquisition system with
  memory
• Answer a few short questions

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Static RAMAn Introduction

• Static RAM is read/write storage that is volatile
• Volatile - when power is removed, contents are
  lost
• Words are written to or read from sites
  determined by the address location under RE/WE
  (read enable/write enable) control
• An 8k x 8 RAM has a 13-bit address bus giving 213
  8192 8-bit locations, or 64kB (65,536)
• A 128k x 8 RAM has a 17-bit address bus, giving
  217 131,072 8-bit locations, or 1MB

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Static RAMRead and Write Timing

• Write Operation
• After the address and data have been stable for a
  setup time, pulse the write enable

A12-0
stable
D7-0
stable
RE
WE
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Static RAMRead and Write Timing

• Read Operation
• Once the address is stable, raise the read enable
• After a settling time, the data is valid

A12-0
stable
WE
RE
D7-0
valid
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What will you do?

• Part 1
• Write two data bytes to two RAM locations and
  read them back
• Learn to display data in hex format in Probe
• Observe Read/Write operations and timing
• Part 2
• Write 8-bit ADC data to 256 locations and read it
  back

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Data Acquisition System Operation

• Repeat n times to store
• Sample an analog signal
• Convert to digital
• Write to the next RAM location
• Repeat n times to retrieve
• Read from next RAM location
• Convert to analog
• Display analog signal
• n number of RAM locations

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Address Generation
DAC
RAM
ADC
Control
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Step 4 - Part 1
RAM8kX8break
DSTM1
R7-0
A16-0
A0
R7
A0
R7
S16
A1
R6
A1
R6
A2
0s 0005 1us 0006 2us 0005 3us 0006 FORMAT4444
R5
A2
R5
A3
R4
A3
R4
A4
R3
A4
R3
A5
R2
A5
R2
A6
R1
A6
R1
A7
FORMAT1111 0s 0000 0.25us 0010 0.75us
0000 1.25us 0010 1.75us 0000 2.00us 0001
R0
A7
R0
A8
A8
A9
W7
A9
W7
A10
W6
A10
W6
FORMAT44 0s 54 1us 36 2us XX
A11
W5
A11
W5
A12
W4
A12
W4
RW3-0
W3
W3
S4
RW0
W2
RE
W2
DSTM2
W7-0
RW1
W1
WE
W1
S8
W0
W0
DSTM3
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Step 4 - Part 1

• Simulate the following activities
• Write data 54H from port W to address 5H
• Write data 36H from port W to address 6H
• Read the contents of address 5H to port R
• Read the contents of address 6H to port R

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Step 4 - Part 2
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Step 4 - Part 2

• Why are the two AND gates (U8A, U12A) needed?
• The address must be set up and stable before the
  WRITE signal is applied

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Step 4 - Part 2
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Step 4 - Part 2
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Step 4 - Part 2

• Simulate the following activities
• Write 8-bit ADC data to the lowest 256 addresses
  in memory
• Read the lowest 256 addresses to the R port
• Generate an analog signal using these 8-bit words

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The 8-Bit Counter

• The 74LS590 binary counter
• Used to generate addresses
• Ripple Carry Out pin makes it easy to set up
  multiple-chip counters

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The 8-Bit CounterMultiple Chips
G
G
LO
LO
CCLK
CCLK
CLK
CCLKEN
RCO
CCLKEN
RCO
A7
A7
RCLK
RCLK
A7
A15
A6
A6
CCLR
CCLR
HI
HI
A6
A14
A5
A5
A5
A13
A4
A4
A4
A12
A3
A3
A3
A11
A2
A2
A2
A10
A1
A1
A1
A9
A0
A0
A0
A8
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RAM Control
RCO
CLK
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Your HardwareStatic RAM

• NEC uPD431000A 128k x 8 Static RAM
• RAM - Random Access Memory
• 128k x 8 - storage for 131,072 8-bit words
• Data is transferred in and out in parallel
• 8-bit tristate data bus
• Input, output, high impedance
• Status controlled by CE1, CE2, WE, OE pins
• Control truth table on datasheet

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Your HardwareStatic RAM

• Address locations
• The 128k x 8 RAM has a 17-bit address bus (217
  131,072)
• You will use the 16 address bits (216 65,536)
  generated by two 74LS590 chips and design a
  simple circuit to provide the 17th address bit
• This gives a total memory of 1024k
• You have the option of using 16 bits for less
  than full credit

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Step 4 Deliverables

• Complete Part 1 Simulation
• Part 1 Schematic
• Part 1 Simulation
• Plot A15-0, W7-0, RW1, RW0, R7-0 vs time
  over span of 0 to 4 us
• Are proper read/write timing rules followed?
• Relationships between address, data, RE, WE
• Is the data read from memory identical to what
  was written?

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Step 4 Deliverables

• Complete Part 2 Simulation
• Part 2 Schematic
• Part 2 Simulation
• Plot W7-0, R7-0, WE, RE, RCO_, AIN, AOUT vs
  time over one complete read/write cycle
• Are proper read/write timing rules followed?
• Relationships between address, data, RE, WE
• Does the data read from memory and converted to
  analog (AOUT) match the input waveform (AIN) to
  the resolution of the system?

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Step 4 Deliverables

• How would you correct the timing flaw at the
  transition from write to read? Repeat the
  simulation with the correction and include the
  results in your report.
• Why is there a lag time in the READ operation
  between the time RE goes high and when the data
  is valid?