ECE 611 Timing - 1

1
Basic Microprocessor Timing

• ECE 611 Microprocessor Systems
• Dr. Roger L. Haggard, Associate Professor
• Department of Electrical and Computer Engineering
• Tennessee Technological University
• Spring 1998

2
68000 Bus Timing - Read
States
Mem/IO Read
(Slow) Mem/IO Read
Bus Cycle
Bus Cycle
S0
S2
S4
S1
S3
S5
S6
S7
S0
S1
S2
S3
S4
W
W
W
W
S5
S6
S7
CLK
3
68000 Bus Timing - Write
Mem/IO Write
(Slow) Mem/IO Write
Bus Cycle
Bus Cycle
S0
S2
S4
S1
S3
S5
S6
S7
S0
S1
S2
S3
S4
W
W
S5
S6
S7
CLK
4
8086 Bus Timing - Read
Two Wait States
States
Mem Read
I/O Input
Bus Cycle
Bus Cycle
T1
T2
T3
T4
T1
T2
T3
Tw
Tw
T4
CLK
(WR is kept high)
5
8086 Bus Timing - Write
One Wait State
Mem Write
I/O Output
Bus Cycle
Bus Cycle
T1
T2
T3
T4
T1
T2
T3
Tw
T4
CLK
(RD is kept high)
6
8051 Timing - Program Memory Read
7
8051 Timing - Data Memory Read
8
8051 Timing - Data Memory Write
9
Memory Interfacing and Timing
10
Interface 68000 to 6116 static RAM (1)
11
6116 (2K x8)
16
A(10-0)
Address bus
Data bus
D00- D07
D(7-0)
Lower byte
A01-A11
RAM1

• 68000
• CPU

A(10-0)
D08- D15
D(7-0)
Upper byte
D00- D15
RAM2
11
Interface 68000 to 6116 static RAM (2)
OE
R/W
6116 (2K x8)
CS
RAM1

• 68000
• CPU

R/W
OE
CS
RAM2
12
Interface 8086 to 6116 static RAM

• 8086

6116 (2K x8)
A(10-0)
A
____ BHE
D(7-0)
__ R/W
low byte (even)
ALE
OE
D
CS
A(10-0)
__ M/IO
D(7-0)
__ R/W
hi byte (odd)
___ WR
___ RD
OE
CS
READY