Slide Title

1
Inverter Layout
2
TX Gate Layout
VDD
C
P
P
Vi
VO
N
N
VSS
C
C
C
For data path structure
3
Transmission Gate Layout
4
NAND Gates Layout
Layout Transistors in Series
Transistors in Parallel
5
NAND Gates Layout
VDD
Via
Metal II
X
A
B
GND
6
NAND Gate Layout
7
Simulation results of CMOS 2-input NAND gate
DC characteristics
 
AC characteristics
8
simulation waveforms of NAND gate
9
NOR Gate Layout
VDD
X
A
B
GND
10
NOR Gate Layout
11
Waveform of the CMOS 2-input NOR gate .
12
Simulation results of CMOS 2-input NOR gate
DC characteristics
AC characteristics
13
Analysis and Design of Complex Gate
Analysis 1. Construct the schematic 2. Determine
the logic function. 3. Determine transistor
sizes. 4. Determine the input pattern to
cause slowest and fastest operations. 5.
Determine the worst case rise delay
(tPLH)and fall delay (tPHL) 6. Determine the best
case rise and fall delays.
A B C
D E
F
VDD
OUT
N-well
GND
A B C
D E
F
14
DFF Layout
15
Fundamental Cell DesignGeneral Considerations

• Static logic
• Select aspect ratio of gates for example

16
Cell Simulation2-input NAND gate
17
2-input NAND gate, Layout
18
2-input NAND gate, Simulation
19
2-input NAND gate, DC Characteristics
Active area (um2) Total area (um2) Static current(uA) VOH (V) VOL (V) VIH (V) VIL (V) NMH (V) NML (V)
3.36 167 0 3.3 0 1.4 0.87 1.9 0.87
20
2-input NAND gate, AC Characteristics
tPLH min (ns) tPHL min (ns) tP min (ns) tPLH max (ns) tPHL max (ns) tP max (ns) tr min (ns) tf min (ns) tr max (ns) tf max (ns) Average power (mW) Peak power (mW)
0.04 0.04 0.04 0.07 0.05 0.06 0.10 0.05 0.12 0.06 2.6 7.5
21
2-input AND gate
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2-input AND gate, layout
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2-input AND gate, simulation
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2-input AND gate, DC Characteristics
Active area (um2) Total area (um2) Static current(uA) VOH (V) VOL (V) VIH (V) VIL (V) NMH (V) NML (V)
5.3 244 0 3.3 0 1.24 1.19 2.06 1.2
25
2-input AND gate, Ac Characteristics
tPLH min (ns) tPHL min (ns) tP min (ns) tPLH max (ns) tPHL max (ns) tP max (ns) tr min (ns) tf min (ns) tr max (ns) tf max (ns) Aver. power (mW) Peak power (mW)
0.13 0.10 0.12 0.15 0.11 0.13 0.10 0.10 0.115 0.105 3.2 7.5
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3-input NAND gate, Design
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3-input NAND gate. layout
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3-input NAND gate, simulation
29
3-input NAND gate, DC Characteristics
Active area (um2) Total area (um2) Static current(uA) VOH (V) VOL (V) VIH (V) VIL (V) NMH (V) NML (V)
5.94 309 0 3.3 0 1.54 0.98 1.76 0.98
30
3-input NAND gate, AC Characteristics
tPLH min (ns) tPHL min (ns) tP min (ns) tPLH max ns tPHL max (ns) tP max (ns) tr min ns tf min (ns) tr max (ns) tf max (ns) Av. power (mW) Peak power (mW)
0.13 0.09 0.11 0.14 0.12 0.13 0.15 0.11 0.16 0.13 3.3 7.9
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3-input AND gate, Design
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3-input AND gate, layout
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3-input AND gate, simulation
34
3-input AND gate, Dc Characteristics
Active area (um2) Total area (um2) Static current(uA) VOH (V) VOL (V) VIH (V) VIL (V) NMH (V) NML (V)
7.86 359. 0 3.3 0 1. 4 1.28 1.9 1.28
35
3-input AND gate, Ac Characteristics
tPLH min (ns) tPHL min (ns) tP min (ns) tPLH max (ns) tPHL max (ns) tP max (ns) tr min (ns) tf min (ns) tr max (ns) tf max (ns) Average power (mW) Peak power (mW)
0.14 0.12 0.13 0.15 0.13 0.14 0.15 0.11 0.15 0.12 3.9 8.9
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2-input NOR gate, Design
37
2-input NOR gate, Layout
38
2-input NOR gate, Simulation
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2-input NOR gate, DC Characteristics
Active area (um2) Total area (um2) Static current(uA) VOH (V) VOL (V) VIH (V) VIL (V) NMH (V) NML (V)
5.76 130 0 3.3 0 1. 53 1.0 1.77 1.0
40
2-input NOR gate, Ac Characteristics
tPLH min (ns) tPHL min (ns) tP min (ns) tPLH max (ns) tPHL max (ns) tP max (ns) tr min ns tf min (ns) tr max (ns) tf max (ns) Av. power (mW) Peak power (mW)
0.10 0.07 0.85 0.11 0.08 0.95 0.15 0.14 0.17 0.15 2.5 5.6
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2-input OR gate, Design
42
2-input OR gate, Layout
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2-input OR gate, Simulation
44
2-input OR gate, DC Characteristics
Active area (um2) Total area (um2) Static current(uA) VOH (V) VOL (V) VIH (V) VIL (V) NMH (V) NML (V)
7.68 220. 0 3.3 0 1. 5 1.41 1.8 1.41
45
2-input OR gate, AC Characteristics
tPLH min (ns) tPHL min (ns) tP min (ns) tPLH max (ns) tPHL max (ns) tP max (ns) tr min (ns) tf min (ns) tr max (ns) tf max (ns) Av. power (mW) Peak power (mW)
0.12 0.11 0.11 0.13 0.12 0.12 0.11 0.13 0.10 0.14 3.0 5.8
46
3-input NOR gate, Design
47
3-input NOR gate, Layout
48
3-input NOR gate, Simulation
49
3-input NOR gate, DC Characteristics
Active area (um2) Total area (um2) Static current(uA) VOH (V) VOL (V) VIH (V) VIL (V) NMH (V) NML (V)
10.8 238. 0 3.3 0 1. 5 1.05 1.78 1.05
50
3-input NOR gate, AC Charcarteristics
tPLH min (ns) tPHL min (ns) tP min (ns) tPLH max (ns) tPHL max (ns) tP max (ns) tr min (ns) tf min (ns) tr max (ns) tf max (ns) Av. power (mW) Peak power (mW)
0.12 0.1 0.1 0.13 0.11 0.12 0.25 0.19 0.31 0.21 4.2 6.9
51
3-input OR gate, Design
52
3-input OR gate, Layout
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3-input OR gate, Simulation
54
3-input OR gate, DC Characteristics
Active area (um2) Total area (um2) Static current(uA) VOH (V) VOL (V) VIH (V) VIL (V) NMH (V) NML (V)
12.7 318. 0 3.3 0 1. 48 1.39 1.82 1.39
55
3-input OR gate, AC Characteristics
tPLH min (ns) tPHL min (ns) tP min (ns) tPLH max (ns) tPHL max (ns) tP max (ns) tr min (ns) tf min (ns) tr max (ns) tf max (ns) Av. power (mW) Peak power (mW)
0.20 0.19 0.19 0.22 0.21 0.21 0.15 0.12 0.16 0.13 4.9 7.8
56
4-input OR gate, Design
57
4-input OR gate, Layout
58
4-input OR gate, Simulation
59
4-input OR gate, DC Characteristics
Active area (um2) Total area (um2) Static current(uA) VOH (V) VOL (V) VIH (V) VIL (V) NMH (V) NML (V)
20.16 401 0 3.3 0 1.5 1.39 1.8 1.39
60
4-input OR gate, AC Characteristics
tPLH min (ns) tPHL min (ns) tP min (ns) tPLH max (ns) tPHL max (ns) tP max (ns) tr min (ns) tf min (ns) tr max (ns) tf max (ns) Av. power (mW) Peak power (mW)
0.30 0.24 0.26 0.34 0.25 0.3 0.12 0.14 0.14 0.15 5.7 12.9
61
2-input XOR gate, Design
62
2-input XOR gate, Layout
63
2-input XOR gate, Simulation
64
2-input XOR gate, DC Characteristics
Active area (um2) Total area (um2) Static current(uA) VOH (V) VOL (V) VIH (V) VIL (V) NMH (V) NML (V)
15.36 381. 0 3.3 0 1.42 1.29 1.88 1.29
65
2-input XOR gate, AC Characteristics
tPLH min (ns) tPHL min (ns) tP min (ns) tPLH max (ns) tPHL max (ns) tP max (ns) tr min (ns) tf min (ns) tr max (ns) tf max (ns) Av. power (mW) Peak power (mW)
0.17 0.14 0.15 0.18 0.15 0.16 0.25 0.20 0.27 0.21 4.7 8.3
66
3-input XOR gate, Design
67
3-input XOR gate, Layout
68
3-input XOR gate, Simulation
69
3-input XOR gate, DC Characteristics
Active area (um2) Total area (um2) Static current(uA) VOH (V) VOL (V) VIH (V) VIL (V) NMH (V) NML (V)
12.5 1237. 0 3.3 0 1.61 1.22 1.69 1.22
70
3-input XOR gate, AC Characteristics
tPLH min (ns) tPHL min (ns) tP min (ns) tPLH max (ns) tPHL max (ns) tP max (ns) tr min (ns) tf min (ns) tr max (ns) tf max (ns) Av. power (mW) Peak power (mW)
0.21 0.19 0.20 0.23 0.20 0.21 0.39 0.20 0.44 0.23 7.7 10.6
71
3-input XNOR gate, Design
72
3-input XNOR gate, Layout
73
3-input XNOR gate, Simulation
74
3-input XNOR gate, DC Characteristics
Active area (um2) Total area (um2) Static current(uA) VOH (V) VOL (V) VIH (V) VIL (V) NMH (V) NML (V)
12.54 1237 0 3.3 0 1.61 1.27 1.69 1.27
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3-input XNOR gate, AC Characteristics
tPLH min (ns) tPHL min (ns) tP min (ns) tPLH max (ns) tPHL max (ns) tP max (ns) tr min (ns) tf min (ns) tr max (ns) tf max (ns) Average power (mW) Peak power (mW)
0.22 0.21 0.21 0.23 0.23 0.23 0.16 0.21 0.17 0.25 7.3 10.1
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Positive-Edge-triggered D Flip-Flop with Reset
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Positive-Edge-triggered D Flip-Flop with Reset
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Positive-Edge-triggered D Flip-Flop with Reset
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Positive-Edge-triggered D Flip-Flop with Reset
parameter minimum typical maximum unit
Clock frequency ------ 1000 1250 MHz
tPLH Reset to Q ------ ------ ------ ns
tPHL Reset to Q 0.35 0.43 0.47 ns
tPLH CLK to Q 0.32 0.34 0.36 ns
tPHL CLK to Q 0.45 0.50 0.53 ns
Width of clock pulse 0.4 0.5 ------ ns
Width of Reset pulse 0.4 1 ------ ns
Setup time 0.3 0.3 0.3 ns
Hold time 0.1 0.1 0.1 ns
Average power dissipation at 1000MHz CLK ------ 0.397 ------ mW
80
Positive-Edge-triggered D Flip-Flop with Preset
81
Positive-Edge-triggered D Flip-Flop with Preset
82
Positive-Edge-triggered D Flip-Flop with Preset
83
Positive-Edge-triggered D Flip-Flop with Preset
parameter minimum typical maximum unit
Clock frequency ------ 1000 1250 MHz
tPLH SET to Q 0.25 0.25 0.26 ns
tPHL SET to Q ------ ------ ------ ns
tPLH CLK to Q 0.30 0.35 0.37 ns
tPHL CLK to Q 0.43 0.47 0.50 ns
Width of clock pulse 0.4 0.5 ------ ns
Width of SET pulse 0.2 0.3 ------ ns
Setup time 0.3 0.3 0.3 ns
Hold time 0.15 0.15 0.15 ns
Average power dissipation at 1000MHz CLK ------ 0.467 ------ mW
84
Positive-Edge-triggered D Flip-Flop with Clear
and Load
85
Positive-Edge-triggered D Flip-Flop with Clear/
Load
86
Positive-Edge-triggered D Flip-Flop with Clear
87
Positive-Edge-triggered D Flip-Flop with Clear
parameter minimum typical maximum unit
Clock frequency ------ 1000 1250 MHz
tPLH CLR to Q ------ ------ ------ ns
tPHL CLR to Q 0.35 0.40 0.43 ns
tPLH CLK to Q 0.35 0.38 0.40 ns
tPHL CLK to Q 0.50 0.57 0.58 ns
Width of clock pulse 0.4 0.5 ------ ns
Width of clear pulse 0.4 0.5 ------ ns
Setup time 0.5 0.5 0.5 ns
Hold time 0.2 0.2 0.2 ns
Average power dissipation at 1000MHz CLK ------ 0.371 ------ mW
88
Positive-Edge-triggered D Flip-Flop with Preset
and Load
89
Positive-Edge-triggered D Flip-Flop with Preset
and Load
90
Positive-Edge-triggered D Flip-Flop with Preset
and Load