AT91SAM7L Enhanced Embedded Flash Controller

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AT91SAM7L Enhanced Embedded Flash Controller
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EEFC Features

• 64KB or 128KB single plane memory organized in
  several pages
• 128-bit wide interface
• Two 128-bit buffers for code read acceleration in
  sequential access
• One write buffer for page programming
• Write buffer size ? Page size
• One lock bit per lock region
• General purpose NVM bits
• Controls specific features in the device
  including Hardware Security Protection

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Embedded Flash Organization

• 128KB Flash
• 512 pages of 256 bytes
• 8 lock regions of 16KB
• Single plane
• 64KB Flash
• 256 pages of 256 bytes
• 16 lock regions of 4KB
• Single plane

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Embedded Flash Performance

• 0 wait state single cycle access up to 17MHz
• 1 wait state up to 30MHz
• 3 wait states up to 37MHz
• 10ms Full Chip Erase
• 2.3ms Page Programming Time
• 4.6ms Page Programming Time including auto-erase

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Sequential Code Read Acceleration

• Two 128-bit prefetch buffers to optimize
  sequential Code Fetch in ARM mode
• In case of sequential reads, the first access
  takes 4 cycles, the other ones only 1 cycle

3WS
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Sequential Data Read Acceleration

• One 128-bit data read buffer to speed up
  sequential Data reads in ARM mode

1WS
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Flash Commands
Command Value Mnemonic
Get Flash Descriptor 0x0 GETD
Write page 0x1 WP
Write page and lock 0x2 WPL
Erase page and write page 0x3 EWP
Erase page and write page then lock 0x4 EWPL
Erase all 0x5 EA
Set Lock Bit 0x8 SLB
Clear Lock Bit 0x9 CLB
Get Lock Bit 0xA GLB
Set GPNVM Bit 0xB SGPB
Clear GPNVM Bit 0xC CGPB
Get GPNVM Bit 0xD GGPB
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Embedded Flash Descriptor

• Command Get Flash Descriptor allows to learn the
  Flash organization
• Suitable for software adaptability when migrating
  to higher Flash density
• Read Flash Result Register after writting the
  GETD command to get Flash information
• MC_FRR
• First read Word 0 FL_ID (Get Flash ID)
• Second read Word 1 FL_Size (Get Flash Size)
• Third read Word 2 FL_Page_Size (Get Flash
  Page Size)

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NVM Bits

• Lock bits protect lock regions from being written
  or erase by inadvertence
• 8 lock bits for the 128KB Flash (16KB)
• 16 lock bits for the 64KB Flash (4KB)
• General Purpose NVM Bits
• GPNVM0 enables the Security Bit
• GPNVM1 defines the memory boot (Flash or bootROM)

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Whats New?

• 128-bit wide memory bus
• No FMCN initialization
• Zero Wait State up to 17MHz
• Sequencial code read acceleration in ARM mode
• New commands
• Get Flash Descriptor, Get Lock Bit Status, Get
  GPNVM Bit Status associated with the Flash Result
  Register
• No dedicated command to enable the security bit
  but GPNVM bit instead
• No NVM bits for BOD