Carry look ahead adder

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Carry look ahead adder

• P (I) a(I) xor b(I)
• G(I) a(I) and b(I)
• S(I) p(I) xor c(I)
• Carry(I1) c(I)p(I) g(I)

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Carry vector

• C(0) cin
• C(1) c(0)p(0) g(0)
• C(2) c(0)p(0)p(1) g(0)p(1)g(1)
• C(3)c(2)p(2) g(2)
• c(0)P(0)p(1)(p2)g(0)p(1)p(2)g(1)p(2)g(2)
• C(4) c(3)p(3) g(3)
• c(0)P(0)p(1)p(2)p(3)g(0)p(1)p(2)p(3)g(1)p(2)p(3
  )g(2)p(3) g(3)

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VHDL code

• entity carrylookadder is
• Port ( a in std_logic_vector(3 downto 0)
• b in std_logic_vector(3 downto 0)
• cin in std_logic
• s out std_logic_vector(3 downto 0)
• cout out std_logic)
• end carrylookadder

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• architecture Behavioral of carrylookadder is
• signal cstd_logic_vector(4 downto 0)
• signal p,g std_logic_vector(3 downto 0)
• begin
• G1 for i in 3 downto 0 generate
• p(i) lt a(i) xor b(i) -- p is a sum of half
  adder
• g(i) lt a(i) and b(i) -- g is a carry of a
  half adder
• s(i) lt p(i) xor c(i) -- s is a sum of the
  full adder
• end generate
• -------Carry look ahead array
• c(0) lt cin
• c(1) lt (cin and p(0)) or g(0) -- c(1)lt
  c(0)and p(0) or g(0)
• c(2) lt (cin and p(0) and p(1)) or (g(0) and
  p(1)) or g(1) -- c(2)lt c(1)and p(1) or g(1)
• c(3) lt (cin and p(0) and p(1) and p(2)) or
  (g(0) and p(1) and p(2)) or (g(1) and p(2)) or
  g(2) --c(3)ltc(2)and p(2) or g(2)
• c(4) lt (cin and p(0) and p(1) and p(2) and
  p(3)) or
• (g(0) and p(1) and p(2) and p(3)) or
• (g(1) and p(2) and p(3)) or
• (g(2) and p(3)) or
• g(3) -- c(3) lt (c(2)and p(2)) or g(2)

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Result