Multi-Cycle CPU

1
Multi-Cycle CPU
2
Multi-Cycle CPU

• Combine Functional Units
• Reuse for different phases of instructions
• One ALU for
• PC increment
• Branch target computation
• Address computation for memory access
• R-Type instruction execution
• One memory unit for both instructions and data
• Multiple but Shorter Clock Cycles
• Different instructions take different number of
  cycles
• Average CPI times cycle time gives better
  performance

3
To Control
31-26
25-0
PCWrite
F
PC 31-28
Zero
Mem Read
Mem Write
D
A
RegWrite
IRWrite
25-21
Read Reg 1
Read/Write Addr
Read Data 1
A
A L U
20-16
Read Reg 2
Memory
Registers
B
Read Data 2
B
Write Reg
Mem Data
4
Write Data
Write Data
15-11
E
C
Mem Data Reg
15-0
5-0
ALUOp
4
To Control
31-26
0 1 2
25-0
PCWrite
PC 31-28
F
Zero
Mem Read
Mem Write
D
A
RegWrite
IRWrite
0 1
0 1
25-21
Read Reg 1
Read/Write Addr
Read Data 1
A
A L U
20-16
Read Reg 2
Memory
Registers
B
0 1
Read Data 2
B
0 1 2 3
Write Reg
Mem Data
4
Write Data
Write Data
15-11
C
0 1
E
Mem Data Reg
15-0
5-0
ALUOp
5
To Control
31-26
0 1 2
25-0
PCWrite
PC 31-28
F
Zero
Mem Read
Mem Write
D
A
RegWrite
PC
IRWrite
0 1
0 1
25-21
Read Reg 1
Read/Write Addr
Read Data 1
A
A L U
20-16
Read Reg 2
Memory
Registers
B
0 1
Read Data 2
B
0 1 2 3
Write Reg
Mem Data
4
Write Data
Write Data
15-11
C
0 1
E
Mem Data Reg
15-0
5-0
ALUOp
ADD
Instruction Fetch/PC Increment
6
To Control
31-26
0 1 2
25-0
PCWrite
PC 31-28
F
Zero
Mem Read
Mem Write
D
A
RegWrite
PC
IRWrite
0 1
0 1
25-21
Read Reg 1
Read/Write Addr
Read Data 1
A
A L U
20-16
Read Reg 2
Memory
IR
Registers
B
0 1
Read Data 2
B
0 1 2 3
Write Reg
Mem Data
4
Write Data
Write Data
15-11
C
0 1
E
Mem Data Reg
Shift Left 2
15-0
Sign Ext
5-0
ALUOp
ADD
Instruction Decode/Register Fetch/Branch Target
7
To Control
PCWriteCond
31-26
0 1 2
25-0
PCWrite
PC 31-28
F
Zero
Mem Read
Mem Write
D
A
RegWrite
PC
IRWrite
0 1
0 1
25-21
Read Reg 1
Read/Write Addr
Read Data 1
A
A L U
20-16
Read Reg 2
ALU Out
Memory
IR
Registers
B
0 1
Read Data 2
B
0 1 2 3
Write Reg
Mem Data
4
Write Data
Write Data
15-11
C
0 1
E
Mem Data Reg
Shift Left 2
15-0
Sign Ext
5-0
ALUOp
SUB
Branch Completion (Branch Taken)
8
To Control
31-26
0 1 2
25-0
Shift Left 2
PCWrite
PC 31-28
F
Zero
Mem Read
Mem Write
D
A
RegWrite
PC
IRWrite
0 1
0 1
25-21
Read Reg 1
Read/Write Addr
Read Data 1
A
A L U
20-16
Read Reg 2
ALU Out
Memory
IR
Registers
B
0 1
Read Data 2
B
0 1 2 3
Write Reg
Mem Data
4
Write Data
Write Data
15-11
C
0 1
E
Mem Data Reg
Shift Left 2
15-0
Sign Ext
5-0
ALUOp
ADD
Instruction Fetch after Branch Completion
9
To Control
31-26
0 1 2
25-0
Shift Left 2
PCWrite
PC 31-28
F
Zero
Mem Read
Mem Write
D
A
RegWrite
PC
IRWrite
0 1
0 1
25-21
Read Reg 1
Read/Write Addr
Read Data 1
A
A L U
20-16
Read Reg 2
ALU Out
Memory
IR
Registers
B
0 1
Read Data 2
B
0 1 2 3
Write Reg
Mem Data
4
Write Data
Write Data
15-11
C
0 1
E
Mem Data Reg
Shift Left 2
15-0
Sign Ext
5-0
ALUOp
ADD
Instruction Decode/Register Fetch/Branch Target
10
To Control
31-26
0 1 2
25-0
Shift Left 2
PCWrite
PC 31-28
F
Zero
Mem Read
Mem Write
D
A
RegWrite
PC
IRWrite
0 1
0 1
25-21
Read Reg 1
Read/Write Addr
Read Data 1
A
A L U
20-16
Read Reg 2
ALU Out
Memory
IR
Registers
B
0 1
Read Data 2
B
0 1 2 3
Write Reg
Mem Data
4
Write Data
Write Data
15-11
C
0 1
E
Mem Data Reg
Shift Left 2
15-0
Sign Ext
5-0
ALUOp
Function
R-Type Instruction Execution
11
To Control
31-26
0 1 2
25-0
Shift Left 2
PCWrite
PC 31-28
F
Zero
Mem Read
Mem Write
D
A
RegWrite
PC
IRWrite
0 1
0 1
25-21
Read Reg 1
Read/Write Addr
Read Data 1
A
A L U
20-16
Read Reg 2
ALU Out
Memory
IR
Registers
B
0 1
Read Data 2
B
0 1 2 3
Write Reg
Mem Data
4
Write Data
Write Data
15-11
C
0 1
E
Mem Data Reg
Shift Left 2
15-0
Sign Ext
5-0
ALUOp

R-Type Instruction Write Back
12
To Control
31-26
0 1 2
25-0
Shift Left 2
PCWrite
PC 31-28
F
Zero
Mem Read
Mem Write
D
A
RegWrite
PC
IRWrite
0 1
0 1
25-21
Read Reg 1
Read/Write Addr
Read Data 1
A
A L U
20-16
Read Reg 2
ALU Out
Memory
IR
Registers
B
0 1
Read Data 2
B
0 1 2 3
Write Reg
Mem Data
4
Write Data
Write Data
15-11
C
0 1
E
Mem Data Reg
Shift Left 2
15-0
Sign Ext
5-0
ALUOp

ADD
Instruction Fetch After R-Type
13
To Control
31-26
0 1 2
25-0
Shift Left 2
PCWrite
PC 31-28
F
Zero
Mem Read
Mem Write
D
A
RegWrite
PC
IRWrite
0 1
0 1
25-21
Read Reg 1
Read/Write Addr
Read Data 1
A
A L U
20-16
Read Reg 2
ALU Out
Memory
IR
Registers
B
0 1
Read Data 2
B
0 1 2 3
Write Reg
Mem Data
4
Write Data
Write Data
15-11
C
0 1
E
Mem Data Reg
Shift Left 2
15-0
Sign Ext
5-0
ALUOp

ADD
Instruction Decode/Register Fetch/Branch Target
14
To Control
31-26
0 1 2
25-0
Shift Left 2
PCWrite
PC 31-28
F
Zero
Mem Read
Mem Write
D
A
RegWrite
PC
IRWrite
0 1
0 1
25-21
Read Reg 1
Read/Write Addr
Read Data 1
A
A L U
20-16
Read Reg 2
ALU Out
Memory
IR
Registers
B
0 1
Read Data 2
B
0 1 2 3
Write Reg
Mem Data
4
Write Data
Write Data
15-11
C
0 1
E
Mem Data Reg
Shift Left 2
15-0
Sign Ext
5-0
ALUOp

ADD
Address Computation (lw or sw)
15
To Control
31-26
0 1 2
25-0
Shift Left 2
PCWrite
PC 31-28
F
Zero
Mem Read
Mem Write
D
A
RegWrite
PC
IRWrite
0 1
0 1
25-21
Read Reg 1
Read/Write Addr
Read Data 1
A
A L U
20-16
Read Reg 2
ALU Out
Memory
IR
Registers
B
0 1
Read Data 2
B
0 1 2 3
Write Reg
Mem Data
4
Write Data
Write Data
15-11
C
0 1
E
Mem Data Reg
Shift Left 2
15-0
Sign Ext
5-0
ALUOp


Memory Access for lw
16
To Control
31-26
0 1 2
25-0
Shift Left 2
PCWrite
PC 31-28
F
Zero
Mem Read
Mem Write
D
A
RegWrite
PC
IRWrite
0 1
0 1
25-21
Read Reg 1
Read/Write Addr
Read Data 1
A
A L U
20-16
Read Reg 2
ALU Out
Memory
IR
Registers
B
0 1
Read Data 2
B
0 1 2 3
Write Reg
Mem Data
4
Write Data
Write Data
15-11
C
0 1
E
Mem Data Reg
Shift Left 2
15-0
Sign Ext
5-0
ALUOp


Write Back for lw
17
To Control
31-26
0 1 2
25-0
Shift Left 2
PCWrite
PC 31-28
F
Zero
Mem Read
Mem Write
D
A
RegWrite
PC
IRWrite
0 1
0 1
25-21
Read Reg 1
Read/Write Addr
Read Data 1
A
A L U
20-16
Read Reg 2
ALU Out
Memory
IR
Registers
B
0 1
Read Data 2
B
0 1 2 3
Write Reg
Mem Data
4
Write Data
Write Data
15-11
C
0 1
E
Mem Data Reg
Shift Left 2
15-0
Sign Ext
5-0
ALUOp


ADD
Instruction Fetch after lw
18
To Control
31-26
0 1 2
25-0
PCWrite
PC 31-28
F
Zero
Mem Read
Mem Write
D
A
RegWrite
IRWrite
0 1
0 1
25-21
Read Reg 1
Read/Write Addr
Read Data 1
A
A L U
20-16
Read Reg 2
Memory
Registers
B
0 1
Read Data 2
B
0 1 2 3
Write Reg
Mem Data
4
Write Data
Write Data
15-11
C
0 1
E
Mem Data Reg
15-0
5-0
ALUOp
19
PCWriteCond
PCSrc
Control
0 1 2
31-26
PCWrite
25-0
PC 31-28
Zero
MemWrite
ALUSrcA
MemRead
IorD
IRWrite
RegDst
RegWrite
0 1
0 1
25-21
Read Reg 1
Read/Write Addr
Read Data 1
A
A L U
20-16
Read Reg 2
Memory
Registers
0 1
Read Data 2
B
0 1 2 3
Write Reg
Mem Data
4
Write Data
Write Data
15-11
0 1
ALUSrcB
Mem Data Reg
15-0
MemtoReg
5-0
ALUOp
20
Control Lines

• PCWriteCond Write PC conditionally on branch
• PCWrite Write PC for increment or
  jump
• PCSrc Select source for writing
  to PC
• IorD Select address for memory
  read/write
• MemRead Read from memory (instruction
  or data)
• MemWrite Write to memory (store word)
• IRWrite Write to Instruction
  Register

21
Control Lines

• MemtoReg Select memory or ALUOut to write to
  register
• RegDst Select field to select
  destination register
• RegWrite Write to selected register
• ALUSrcA Select source for upper ALU input
• ALUSrcB Select source for lower ALU input
• ALUOp Select ALU operation or set to
  function
• code 00 Add, O1
  Subtract,
• 10 use funct
  field (bits 0-5)

22
Clock Cycles

• 1. Instruction Fetch, PC Increment
• 2. Instruction Decode, Register Fetch,
• Branch Target Computation
• 3. R-type Execution or
• Memory Address Computation or
• Branch Completion
• 4. R-type Write Back or
• Memory Access
• 5. Memory write back

23
Control Overview
Instruction Fetch
Instruction Decode
Start
Memory Access
R-type
Branch
Jump
24
Control Finite State Machine
Instruction Fetch 0
Instruction Decode 1
MemRead IorD 0 IRWrite ALUSrcA 0 ALUSrcB
01 ALUOp 00 PCSrc 00 PCWrite
ALUSrcA 0 ALUSrcB 11 ALUOp 00
Start
lw or sw
R-type
beq
j
Memory Access FSM
Branch FSM
Jump FSM
R-type FSM
25
Memory Access FSM
Memory Address Comp 2
From State 1 lw or sw
ALUSrcA 1 ALUSrcB 10 ALUOp 00
Memory Access lw 3
lw
sw
MemRead IorD 1
MemWrite IorD 1
Memory Access sw 5
Write Back 4
RegWrite MemToReg 1 RegDst 0
To State 0
26
R-type FSM
From State 1 R-type
ALUSrcA 1 ALUSrcB 00 ALUOp 10
Execution 6
RegDst 1 RegWrite MemtoReg 0
Write Back 7
To State 0
27
Branch FSM
From State 1 beq
ALUSrcA 1 ALUSrcB 00 ALUOp
01 PCWriteCond PCSrc 01
Branch Completion 8
To State 0
28
Jump FSM
From State 1 j
PCWrite PCSrc 10
Jump Completion 9
To State 0
29
Complete Finite State Machine
Instruction Fetch 0
Instruction Decode 1
MemRead IorD 0 IRWrite ALUSrcA 0 ALUSrcB
01 ALUOp 00 PCSrc 00 PCWrite
ALUSrcA 0 ALUSrcB 11 ALUOp 00
Start
lw or sw
R-type
j
beq
ALUSrcA 1 ALUSrcB 10 ALUOp 00
Memory Address Comp 2
ALUSrcA 1 ALUSrcB 00 ALUOp 10
Execution 6
Jump Completion 9
PCWrite PCSrc 10
lw
sw
Memory Access lw 3
MemRead IorD 1
Branch Completion 8
ALUSrcA 1 ALUSrcB 00 ALUOp
01 PCWriteCond PCSrc 01
MemWrite IorD 1
RegDst 1 RegWrite MemtoReg 0
Memory Access sw 5
Write Back 7
RegWrite MemToReg 1 RegDst 0
Write Back 4
30
FSM Implementation as PLA
PLA
Opcode from IR
Clock
State Register
PCWrite
ALUOp
PCWriteCond
ALUSrcB
PCSrc
IorD
ALUSrcA
MemRead
RegWrite
MemWrite
RegDst
IRWrite
MemtoReg