Title: RTL Design Methodology
1Lecture 19 RTL Design Methodology SORTING
example
2Structure of a Typical Digital System
Data Inputs
Control Inputs
Control Signals
Datapath (Execution Unit)
Controller (Control Unit)
Status Signals
Data Outputs
Control Outputs
3Hardware Design with RTL VHDL
Interface
Pseudocode
Datapath
Controller
ASM chart
Block diagram
VHDL code
VHDL code
4Steps of the Design Process
- Text description
- Interface
- Pseudocode
- Block diagram of the Datapath
- Interface divided into Datapath and Controller
- ASM chart of the Controller
- RTL VHDL code of the Datapath, Controller, and
Top-Level Unit - Testbench for the Datapath, Controller, and
Top-Level Unit - Functional simulation and debugging
- Synthesis and post-synthesis simulation
- Implementation and timing simulation
- Experimental testing using FPGA board
5Steps of the Design ProcessIntroduced in Class
Today
- Text description
- Interface
- Pseudocode
- Block diagram of the Datapath
- Interface divided into Datapath and Controller
- ASM chart of the Controller
- RTL VHDL code of the Datapath, Controller, and
Top-level Unit - Testbench for the Datapath, Controller, and
Top-Level Unit - Functional simulation and debugging
- Synthesis and post-synthesis simulation
- Implementation and timing simulation
- Experimental testing using FPGA board
6SORTING example
7Sorting - Required Interface
8Sorting - Required Interface
9Simulation results for the sort operation
(1)Loading memory and starting sorting
10Simulation results for the sort operation
(2)Completing sorting and reading out memory
11Sorting - Example
During Sorting
After sorting
Before sorting
i0 i0 i0 i1 i1 i2 j1 j2 j3 j2 j3 j3
Address
0 1 2 3
3 3 2 2 1 1 1 1 2 2 3 3 3 3 2 2 4 4 4 4 4 4 4 3
1 1 1 1 2 2 3 4
Legend
position of memory indexed by i
position of memory indexed by j
Mj
Mi
12Pseudocode
FOR k 4
FOR any k 2
load input data wait for s1
load input data wait for s1
for
i
0
to
2
do
-
for
i
0
to
k
2
do
Mi
A
Mi
A
for
j
i
1
to
3
do
for
j
i
1
to
k
1
do
B
Mj
B
Mj
if
B
lt
A
then
if
B
lt
A
then
Mi
B
Mi
B
Mj
A
Mj
A
A
Mi
A
Mi
endif
endif
endfor
endfor
endfor
endfor
Done wait for s0 read output data go to the
beginning
Done wait for s0 read output data go to the
beginning
13Pseudocode
- wait for s1
- for i0 to k-2 do
- A Mi
- for ji1 to k-1 do
- B Mj
- if A gt B then
- Mi B
- Mj A
- A Mi
- end if
- end for
- end for
- Done
- wait for s0
- go to the beginning
14SORTING solutions
15DataIn
RAdd
0
ABMux
N
L
L
N
LD
Li
Resetn
0
1
s
EN
RST
Ei
CLK
Din
s
Clock
1
Csel
WrInit
DIN
We
LD
Lj
WE
0
Resetn
L
Addr
EN
RST
Ej
i
Wr
ADDR
0
CLK
Clock
CLK
1
Clock
L
L
j
DOUT
1
N
Mij
k-1
EA
EB
k-2
Resetn
Resetn
EN
RST
CLK
Clock
Clock
Rd
zi
zj
N
N
N
Bout
1
0
B
A
DataOut
AgtB
Block diagram of the Datapath
AgtB
16Interface with the division into Datapath and
Controller
DataIn
Clock
Resetn
WrInit
s
RAddr
Rd
N
L
AgtB
zi
zj
Datapath
Controller
Wr Li Ei Lj Ej EA EB Bout Csel
N
DataOut
Done