High%20End%20Computing

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High End Computing

• Graphics Hardware and Software Architectures

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Presentation Overview

• Short History
• Today
• High End Computer Architecture
• Specialized Graphics Hardware
• Software Architecture Instantiated

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Short History

• Federally sponsored University research began in
  1965
• Ivan Sutherland and Jim Clark
• New technologies make graphics accessible
• VLSI chips
• High Level Programming Languages
• Less expensive HW led to growing market
• Jim Clark developed Geometry Engine
• Founded SGI (Silicon Graphics Inc.)

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Today

• SGI is an industry leader
• High Performance Graphics Computer Development
• Our Example Onyx2 InfiniteReality2
• Designed to provide system support for OpenGL

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High End Computer ArchitectureOnyx2
InfiniteReality2

• ccNUMA (Cache Coherent Non Uniform Memory Access)
  Architecture
• Automatic scaling of system and graphics
  bandwidth
• Low transport latency
• Continuous, real-time fly-overs of large terrain
• Support interactive, immersive visualization of
  unbounded volumes (Visible Human)

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Onyx2 InfiniteReality2 cont.
XIO
XIO
XIO
Router
Router
Router
Interconnection fabric
Router
XIO
Router
Router
XIO
XIO
ccNUMA Diagram
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Onyx2 InfiniteReality2 cont.
Graphics
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Graphics Hardware
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Graphics Pipeline

• Supports primitives
• Polygons
• Vectors
• Points
• Parametric polynomial surfaces
• Primitives combine
• Mesh polygon strips with common vertices

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Geometry Board
Crossbow
Geometry Board
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Raster Manager
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Display Generator
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Cosmic Head
http//www.realshades.com/3D/gallery/3D-001.html
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Software ArchitectureOpenGL

• Multi-platform industry standard graphics library
• A state machine
• Native graphics programming interface for Onyx2
  InfiniteReality2
• Implemented within graphics subsystem

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Fragment Operations
Unpack Vertices Unpack / Pack Pixels
Texture Memory Operations
Vertex Operations Pixel Operations
Frame buffer
Point, Line, Polygon Rasterization Image
Rasterization
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Software Architecture Mapped Over Hardware
Architecture
Geom. Dist.
Frag. Gen.
Fragment Processing
HIP
GE16
TMEM
Frame buffer
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Some Specifications of Onyx2 Infinite Reality2

• Two or four 4MB cache MIPS R10000 processors
• 128MB to 8GB of memory
• Single graphics pipeline with one or two Raster
  Managers
• 64MB of texture memory
• Up to 160MB of frame buffer capacity

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Mips R10000

• This processor features a four-way superscalar
  RISC processor that
• fetches and decodes four instructions per cycle,
• speculatively executes beyond branches, with a
  four-entry branch stack,
• uses dynamic out-of-order execution,
• implements register renaming using map tables,
  and
• achieves in-order graduation for precise
  exceptions.

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