MVSIS Group

1
Optimization of Multi-Valued Multi-Level Networks

• MVSIS Group
• Minxi Gao,, Jie-Hong Jiang, Yunjian Jiang,
  Yinghua Li, Alan Mishchenko1, Subarna Sinha,
• Tiziano Villa2, and Robert Brayton
• Dept. of Electrical Engineering and Computer
  Science University of California, Berkeley

1 Portland State Univ., Portland OR 2 Parades,
Rome, Italy
2
Outline

• Motivations From binary to multi-value
• MV Networks Design specification
• MVSIS optimizations
• Node simplification
• Algebraic extraction
• Pairing merging and encoding
• Network manipulations
• Demo
• New capabilities
• Conclusions

3
Motivations

• Synchronous binary hardware synthesis
• Software synthesis from synchronous
  specifications
• Asynchronous hardware synthesis
• Multi-valued devices?
• Current-mode CMOS devices
• Optical logic circuits

4
Motivation synchronous hardware

• Design and synthesis from multi-valued logic
• MV is natural method of specification
• Larger design space

5
Motivation software synthesis

• Synchronous programming of embedded systems
• Esterel/Lustre/Signal
• Interactive FSM semantics
• Code generation from logic

6
Motivation multi-valued devices

• Multi-valued current-mode MOS
• signed digit arithmetic
• High-speed, Low supply voltage

Building blocks
Current source Linear sum PMOS current mirror Threshold detector

Iy
Ix
IT
x
y1
y2
T. Hanyu and M. Kameyama, A 200 MHz pipelined
multiplier using 1.5 V-supplymultiple-valued MOS
current-mode circuits with dual-rail
source-coupled logic, IEEE Journal of
Solid-Statee Circuits, 1995 A. Jain, R. Bolton
and M. Abd El-Barr, CMOS Multi-Valued Logic
Design, IEEE Trans. on Circuits and Systems,
Aug. 1993.
7
Functional Semantics(MV-Network)
F

• Network of MV-nodes
• Each variable xn has its own range0, 1,,
  pn-1
• Values are treated uniformly
• MV-literal x0,2
• MV-cube x0,2z0,1
• MV-relation at each node (can be
  non-deterministic)

Latch
8
Design Specification
blif-mv
.model simple .inputs a b .outputs f .mv f 3 .mv
x 3 .table x a b -gt f .def 0 0 1 1 1 1,2
0 - 1 1 - 1 2 0 - 0 2 ... .reset
x 0 .latch f x ... .exdc .inputs a b .outputs
f .table a b -gt f .def 0 0 0 1 .end

• BLIF-MV subset
• Single output MV nodes
• Can be non-deterministic
• Flat network, no hierarchy (yet)
• Constant initial states (.reset)
• Extensions
• External dont care networks (.exdc)
• Can have an external dont care specified for
  each output
• Can specify datapaths

9
MVSIS Optimization

• MVSIS optimizations
• Node simplification
• Kernel and cube extraction/decomposition
• Pairing/Merging
• Encoding
• Network manipulations

10
MV-SOP Minimizers

• For each i-set (MV-input, binary output)
• Two-level Espresso-MV
• minimize an i-set with a dont care.
• a dont care is an input for which the output can
  be any value.
• Two-Level ISOP (Minato)
• Fast method to build a cover of cubes of an i-set
  from MDD of function and MDD of dont cares
  (method of Minato extended to MV).
• All i-sets at once
• Quine-McCluskey type ND minimization
• Given a ND relation, generate a cover of all
  i-sets such that the total number of cubes is
  minimum.

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Node Simplification
mvsisgt simplify mvsisgt fullsimp mvsisgt
reset_default

• Multi-level (using dont cares - inputs for which
  output can be any value)
• Compatible observability dont cares(CODC)
• Satisfiability dont cares (SDC)
• External dont cares (XDC)
• Generalization from binary case

Reference Y. Jiang et. al. Compatible
Observable Dont Cares for MV Logic, ICCAD01
12
Node Simplification
mvsisgt complete_simplify -m ISOP, ESP, QM

• Using non-determinism
• Derive Complete Flexibility at a node (an ND
  relation)
• Minimize ND relation
• Espresso
• ISOP
• QM
• Automatically finds best default
• Uses external specification (relation)

Reference A. Mishchenko and R. Brayton,
Simplification of Non-Deterministic MV
Networks, IWLS, June 2002.
13
Computing Complete Flexibility at a node
The complete flexibility at node j is
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Quine-McCluskey type ND relation minimization

• Given an ND relation, e.g. the complete
  flexibility, its i-set is the set of input
  minterms that can produce output value i.
• Generate for each i-set all its primes, Pi
• Form covering table with one column for each pj
  in Pi for all i
• One row for each minterm in the input space
• Solve minimum covering problem
• Primes chosen from each Pi is the cover for each
  i-set.

15
Algebraic Decompositions
Example factoring/ decomposition/resub

• Kernel extraction
• Semi-algebraic division
• Resubstitution
• Factoring/Decomposition

-q Two-cube divisors -g Best divisors
F a0,1,2 c3 b1,2,3 c3
a0b1,2,3 c0 a0 c1
(c3 a0c0,1) (a0,1,2 c1,3 b1,2,3
c0,3)
mvsisgt fx -q -g mvsisgt resub mvsisgt
decomp mvsisgt factor
M. Gao and R. K. Brayton, Multi-valued
Multi-level Network Decomposition, IWLS, June
2001.
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EBD Algebraic Decompositions
mvsisgt ebd_fx mvsisgt ebd_decomp

• Stands for Encode, Binary, Decode
• Use binary codes to encode
  multi-valued variable x, e.g
• Operate with fast binary implementations imported
  from SIS
• Convert (decode) back to multi-valued

J-H Jiang, A. Mishchenko, R. Brayton, Reducing
Multi-Valued Operations to Binary, IWLS02
Results Quality almost as good, but much faster
17
Pairing Merging and Encoding

• Pair_decode/Merge
• Combine two or more nodes
• into a single node with more values.
• Explore different combinations
• Encode
• full and partial encode
• Combine some i-sets
• combine i-sets where those values
• always appear together in fanouts.

mvsisgt pair_decode mvsisgt merge mvsisgt encode
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Other Commands

• Network manipulations
• mvsisgt eliminate
• mvsisgt collapse
• mvsisgt sweep
• IO interface
• mvsisgt read(write)_blifmv
• mvsisgt read(write)_blif
• Verification
• mvsisgt validate -n (uses simulation)
• mvsisgt verify
• mvsisgt gen_vec
• mvsisgt simulate
• mvsisgt qcheck (quick check for ND network)

• Printing
• mvsisgt print
• mvsisgt print_stats
• mvsisgt print_factor
• mvsisgt print_range
• mvsisgt print_io
• mvsisgt print_value
• Sequential
• mvsisgt extract_seq_dc

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Design Flow

• Typical design flow

mvsisgt source mvsis.script (general MV
script) mvsisgt encode -i mvsisgt source
mvsis.scriptb (keeps all nodes binary)
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Example 1 Matrix multiplication (3 values)
2 X 2 matrix mult over the ring Z_3 .model
matmul .inputs a11 a12 a21 a22 .inputs b11
b12 b21 b22 .outputs c11 c12 c21 c22 .mv
a11, a12, a21, a22 3 .mv b11, b12, b21,
b22 3 .mv c11, c12, c21, c22 3 .table a11
a12 b11 b21 c11 0 0 - - 0 0 1 - - b21 0 2 - 0
0 0 2 - 1 2 0 2 - 2 1 1 0 - - b11 1 1 0 0
0 1 1 0 1 1 1 1 0 2 2 1 1 1 0 1 .table a11
a12 b12 b22 c12 0 0 - - 0 0 1 - - b22 0 2 - 0
0 0 2 - 1 2 0 2 - 2 1
1 0 - - b12 1 1 0 0 0 1 1 0 1 1 1 1 0 2 2
.table a21 a22 b11 b21 c21 0 0 - - 0 0 1 - -
b21 0 2 - 0 0 0 2 - 1 2 0 2 - 2 1 1 0 - -
b11 1 1 0 0 0 1 1 0 1 1 1 1 0 2 2 1 1 1 0
1 1 1 1 1 2 1 1 1 2 0 1 1 2 0 2 1 1 2 1 0 1 1
2 2 1 1 2 0 0 0 1 2 0 1 2 1 2 0 2 1 1 2 1 0
1 1 2 1 1 0
.table a21 a22 b12 b22 c22 0 0 - - 0 0 1 - -
b22 0 2 - 0 0 0 2 - 1 2 0 2 - 2 1 1 0 - -
b12 1 1 0 0 0 1 1 0 1 1 1 1 0 2 2 1 1 1 0
1 .end
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Demo

1. simulated
2. live

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cadntws11/home/wjiang/mvsis/examples/bob
mvsis UC Berkeley, MVSIS mvsisgt help alias
chng_name collapse
decomp delete
echo
elim_part eliminate
encode extract_seq_dc
factor fullsimp
fx gen_vec
help history
merge
pair_decode print
print_altname print_factor
print_io print_level
print_part_value print_range
print_stats print_value
qcheck quit
read_blif
read_blifmv reset_default
reset_name resub
runtime set
simplify simulate
source sweep
unalias undo
unset usage
validate
write_blifmv mvsisgt
mvsisgt read_blifmv matmul-c mvsisgt
mvsisgt chng_name changing to short-name mode
mvsisgt print_stats matmul 4 nodes, 4 POs, 128
cubes(sop), 480 lits(sop) mvsisgt
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mvsisgt print_io primary inputs a b c d e f g
h primary outputs i j k l mvsisgt
mvsisgt set autoexec pfs matmul 4 nodes, 4 POs,
128 cubes(sop), 480 lits(sop), 216
lits(fact.) mvsisgt
mvsisgt print_range i 3 j 3 k 3 l 3 a
3 b 3 c 3 d 3 e 3 f 3 g 3 h 3 matmul 4
nodes, 4 POs, 128 cubes(sop), 480 lits(sop),
216 lits(fact.) mvsisgt
mvsisgt simplify matmul 4 nodes, 4 POs, 96
cubes(sop), 320 lits(sop), 160
lits(fact.) mvsisgt
mvsisgt reset_default matmul 4 nodes, 4 POs,
96 cubes(sop), 320 lits(sop), 160
lits(fact.) mvsisgt
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mvsisgt fullsimp matmul 4 nodes, 4 POs, 96
cubes(sop), 320 lits(sop), 160
lits(fact.) mvsisgt
mvsisgt pair_decode 1 m0 a0e2 e0 m1
a0e1 m3 a1e2 a2e1 n0
a0f2 f0 n1 a0f1 n3 a1f2
a2f1 o0 e0c2 c0 o1
e0c1 o3 e1c2 e2c1 p0
f0c2 c0 p1 f0c1 p3 f1c2
f2c1 q0 b0g2 g0 q1
b0g1 q3 b1g2 b2g1 r0
b0h2 h0 r1 b0h1 r3 b1h2
b2h1 s0 g0d2 d0 s1
g0d1 s3 g1d2 g2d1 t0
h0d2 d0 t1 h0d1 t3 h1d2
h2d1 matmul 12 nodes, 4 POs, 64
cubes(sop), 184 lits(sop), 160
lits(fact.) mvsisgt
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mvsisgt simplify matmul 12 nodes, 4 POs, 56
cubes(sop), 96 lits(sop), 96 lits(fact.) mvsisgt
mvsisgt reset_default matmul 12 nodes, 4 POs,
56 cubes(sop), 96 lits(sop), 96
lits(fact.) mvsisgt
mvsisgt fullsimp matmul 12 nodes, 4 POs, 56
cubes(sop), 96 lits(sop), 96 lits(fact.) mvsisgt
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mvsisgt print_factor i1 m2q2 m1q0
m0q1 i2 m2q0 m1q1
m0q2 j1 n2r2 n1r0
n0r1 j2 n2r0 n1r1
n0r2 k1 o2s2 o1s0
o0s1 k2 o2s0 o1s1
o0s2 l1 p2t2 p1t0
p0t1 l2 p2t0 p1t1
p0t2 m0 a0 e0 m2 a2e1
a1e2 n0 a0 f0 n2 a2f1
a1f2 o0 c0 e0 o2 c2e1
c1e2 p0 c0 f0 p2 c2f1
c1f2 q0 b0 g0 q2 b2g1
b1g2 r0 b0 h0 r2 b2h1
b1h2 s0 d0 g0 s2 d2g1
d1g2 t0 d0 h0 t2 d2h1
d1h2 matmul 12 nodes, 4 POs, 56
cubes(sop), 96 lits(sop), 96 lits(fact.) mvsisgt
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mvsisgt validate -m mdd matmul-c Networks are
combinationally equivalent according to MDD
method. matmul 12 nodes, 4 POs, 56
cubes(sop), 96 lits(sop), 96 lits(fact.) mvsisgt
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cadntws11/home/wjiang/mvsis/examples/bob
mvsis UC Berkeley, MVSIS mvsisgt mvsisgt
read_blifmv red-add.mv mvsisgt
mvsisgt chng_name changing to short-name
mode mvsisgt
mvsisgt print_io primary inputs a b c d
e primary outputs f g h mvsisgt
mvsisgt set autoexec pfs red_adder 3 nodes, 3
POs, 48 cubes(sop), 240 lits(sop), 69
lits(fact.) mvsisgt
mvsisgt reset_default red_adder 3 nodes, 3 POs,
48 cubes(sop), 240 lits(sop), 69
lits(fact.) mvsisgt
mvsisgt simplify red_adder 3 nodes, 3 POs, 15
cubes(sop), 44 lits(sop), 28 lits(fact.) mvsisgt
mvsisgt fullsimp red_adder 3 nodes, 3 POs, 15
cubes(sop), 44 lits(sop), 28 lits(fact.) mvsisgt
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mvsisgt print_range f 2 g 2 h 2 a 8 b 8
c 8 d 8 e 8 red_adder 3 nodes, 3 POs, 15
cubes(sop), 44 lits(sop), 28 lits(fact.) mvsisgt
mvsisgt encode red_adder 3 nodes, 3 POs, 15
cubes(sop), 44 lits(sop), 28 lits(fact.) mvsisgt
mvsisgt print_range f 2 o 2 g 2 p 2 h
2 q 2 i 2 r 2 j 2 s 2 k 2 t 2 l 2 u
2 m 2 v 2 n 2 w 2 red_adder 3 nodes, 3
POs, 15 cubes(sop), 44 lits(sop), 28
lits(fact.) mvsisgt
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mvsisgt simplify red_adder 3 nodes, 3 POs, 15
cubes(sop), 44 lits(sop), 28 lits(fact.) mvsisgt
mvsisgt fullsimp red_adder 3 nodes, 3 POs, 15
cubes(sop), 44 lits(sop), 28 lits(fact.) mvsisgt
mvsisgt print_io primary inputs i j k l m n o p
q r s t u v w primary outputs f g
h red_adder 3 nodes, 3 POs, 15 cubes(sop),
44 lits(sop), 28 lits(fact.) mvsisgt
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mvsisgt read_blifmv red-add.mv red_adder 3
nodes, 3 POs, 48 cubes(sop), 240 lits(sop),
69 lits(fact.) mvsisgt
mvsisgt help encode Feb 16, 2001
MVSIS(1)
encode -i -n -s Encode the whole
network into a binary one, considering both
output and input constraints. For
sequential networks, a latch is encoded with
constraints generated from both its inputs and
outputs -i keep primary inputs and
outputs as multi-valued add interface
nodes between the internal encoded binary network
and PI/POs. This option allows
validation of the result. -n use natural
code -s use NO_COMP rather than ESPRESSO
as the intermediate minimization
method. The difference is only in performance.
Ordinary users should not be concerned
with this option. red_adder 3 nodes, 3 POs,
48 cubes(sop), 240 lits(sop), 69
lits(fact.) mvsisgt
mvsisgt encode -n red_adder 3 nodes, 3 POs,
1251 cubes(sop), 9432 lits(sop), 577
lits(fact.) mvsisgt
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mvsisgt simplify -t 1000 red_adder 3 nodes, 3
POs, 315 cubes(sop), 2010 lits(sop), 156
lits(fact.) mvsisgt
mvsisgt simplify -t 1000 -m exact red_adder 3
nodes, 3 POs, 300 cubes(sop), 1989 lits(sop),
130 lits(fact.) mvsisgt
mvsisgt validate -m mdd red-add-bin.mv Networks
differ on (at least) primary output s1 i-set
0 Incorrect input is 0 x1_b0 1 x1_b1 1 x1_b2 0
x0_b0 0 x0_b1 0 x0_b2 0 y1_b0 0 y1_b1 0 y1_b2 0
y0_b0 0 y0_b1 0 y0_b2 0 cin_b0 0 cin_b1 0
cin_b2 Networks are NOT combinationally
equivalent. red_adder 3 nodes, 3 POs, 300
cubes(sop), 1989 lits(sop), 130
lits(fact.) mvsisgt
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New Capabilities

• Non-deterministic MV Networks
• Post Networks
• Delay Insensitive Asynchronous Synthesis

34
Non-Deterministic Networks

• Any node can be an ND relation
• The behavior (relation between inputs and
  outputs) of the network is that obtained by
  collapsing the network in topological order.
• Use of complete flexibility at a node can
  increase the behavior

35
Non-Deterministic Networks

• Example implies that need a theory of ND
  networks.
• In general, behavior can increase when network
  is manipulated
• MVSIS allows non-determinism at each node
• However, we have never seen a final network that
  did not satisfy its specifications.

36
Post Networks

• Use chain-based Post algebra for each node
  expression.
• Let m be the maximum value. A literal
• Note that
• New factorization algorithm for MIN, MAX
  expressions.

37
Synthesis of Asynchronous Delay Insensitive
Circuits

• Direct synthesis from synchronous language
  (Verilog)
• Have to implement all i-sets, i.e. all variables
  are implemented 1-hot
• All final circuits are binary
• All variables have to be acknowledged by special
  acknowledgement circuit which generate done
  signal.
• Use of MV variables saves power/area

38
Conclusions

• MV logic networks important in various
  applications
• Presented MVSIS, an multi-valued logic synthesis
  software infrastructure
• Release 1.1 on Linux and Windows platforms (as of
  May, 2002)
• Support registers
• External and sequential dont cares
• Verification based on MDD representations
• software generation from Esterel
• use of complete flexibility
• non-determinism

http//www-cad.eecs.berkeley.edu/Respep/Research/m
vsis free download (binary versions available on
Windows, Unix)
39
Some Recent Publications

• Multi-Valued Logic Optimization on Post Logic
  Networks submitted to ICCAD 2002
• Dont Care Computations in Minimizing Extended
  Finite State Machines with Presburger Arithmetic
  IWLS 2002
• Software Synthesis from Synchronous
  Specifications Using Logic Simulation Techniques
  DAC 2002

• Simplification of Non-Deterministic Multi-Valued
  Networks IWLS 2002
• A Boolean Paradigm in Multi-Valued Logic
  Synthesis IWLS 2002

40
Thank You
41
Motivation multi-valued devices

• MIN operator

N
current mirror
x
P
x
min(x,y)
N
N
I1
I2gt0
I3
I4
y
A. Jain, R. Bolton and M. Abd El-Barr, CMOS
Multi-Valued Logic Design, IEEE Trans. on
Circuits and Systems, Aug. 1993.