Digital Components

1
Digital Components

• Computer Architecture and Design
• Lecture 2

2
Digital Components

• To understand the organization and design of
  digital computers, it is very important to be
  familiar with the various digital components
  widely used.
• Digital components means digital circuits, and
  digital circuits are constructed with integrated
  circuits.

3
Integrated Circuits

• A small silicon semiconductor device, called a
  chip, containing electronic
  components for the gates connected by wires.
• 14 to 1000 or more pins
• Numeric designation printed on surface of the
  package
• Vendors publish data books or catalogues

Usage
No. Gates
Name
SSI (Small-scale integration)
Gates
10
Decoders, adders, registers
MSI (Medium-scale integration)
10 - 200
Processors, Memory chips
200 - few thousands
LSI (Large-scale integration)
Complex microcomputer
VLSI (Very Large-scale integration)
Thousands -
4
Digital Logic Family FYI.

• TTL (Transistor- Transistor Logic)
• Bipolar transistor based circuits
• ECL (Emitter- Coupled Logic)
• High-speed digital circuits Supercomputers,
  signal processors
• MOS (Metal-Oxide Semiconductor)
• Unipolar transistor (Bipolar Tr. TTL, ECL)
• NMOS (n-channel MOS) PMOS (p-channel MOS)
• CMOS (Complementary MOS)
• PMOS NMOS connected in complementary fashion
• High-packing density than bipolar
• Simpler processing technique than bipolar
• Economical operation due to low-power

5
In This Class

• We stay at logic level which is independent of
  circuit technology.
• We now review most popular digital components
  which will be essential for your mini-CPU in near
  future.

6
Decoder

• n-to-m-line (n x m) decoder is a combinational
  circuit that converts n coded inputs to a maximum
  of m2n unique outputs

A2
000
D0
A1
Outputs
Inputs
Enable
001
D1
A0
D7
A0
D6
D5
D4
A1
A2
E
D3
D2
D1
D0
010
D2
0
x
0
0
0
x
x
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
011
D3
0
1
0
0
0
0
0
1
0
0
0
1
100
0
0
0
0
0
1
0
1
0
0
0
1
D4
0
1
0
0
0
1
0
1
0
0
0
1
101
D5
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
1
1
0
0
0
0
1
110
D6
0
0
0
0
1
1
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
1
111
D7
Enable(E)
7
Encoder

• A 2n-to-n encoder takes 2n inputs ranged 0 to 2n
  -1 and generates an n-bit binary equivalent

Outputs
Inputs
D0
A0
A1
A2
D7
D6
D5
D4
D3
D2
D1
D0
A0
D1
0
0
0
0
0
0
0
0
0
0
1
D2
1
0
0
0
0
0
0
0
0
0
1
D3
A1
0
1
0
0
0
0
0
0
0
0
1
D4
1
1
0
0
0
0
0
0
0
0
1
D5
0
0
1
0
0
0
0
0
0
0
1
D6
A2
1
0
1
0
0
0
0
0
0
0
1
D7
0
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
8
Multiplexor (MUX)

• A 2nx1 multiplexer with n selection lines takes
  2n inputs and outputs only one of them according
  to the selection line combinations

I0
Output
Select
I1
Y
S1
S0
Y
I2
I0
0
0
I3
I1
1
0
I2
1
0
I3
1
1
S0
S1
9
Register

• An n bit register has a group of n flip-flops and
  gates is capable of storing n-bit binary
  information and data processing
• Simplest register is a single flip-flop
• Ex 4-bit register on the right.

A0
I0
Q
D
C
Clock
A1
I1
Q
D
C
A2
I2
Q
D
C
A3
I3
Q
D
C
Clear
10
Register with Parallel Load
Load
A0
D
Q
C
I0
D
A1
Q
C
I1
A2
D
Q
C
I2
D
A3
Q
C
I3
Clock
11
when load 1
Load
Data Path due to parallel load
A0
D
Q
C
I0
Data moving thru data path
D
A1
Q
C
I1
A2
D
Q
C
I2
A3
D
Q
C
I3
Clock
12
when load 0
Load
Data Path due to parallel load
A0
D
Q
C
I0
Data moving thru data path
D
A1
Q
C
I1
A2
D
Q
C
I2
A3
D
Q
C
I3
Clock
13
Verilog Homework 1

• Design Register with Parallel Load using
  Verilog and do the Simulation.
• Use Structural Code and Behavioral Code.
• TA will determine the due date and collect the
  following from you. 1) DUT, 2) Testbench and 3)
  Simulation Output Waveform.

14
Shift Register

• A register capable of shifting its binary
  information in one or both directions

Serial Input
Serial Output
Clock
15
Bidirectional Shift Register with Parallel Load

• A register capable of shifting its binary
  information in both directions parallel data
  loading

Mode
Register Op.
S1
S0
No Change
0
0
Shift right (down)
1
0
Shift left (up)
1
0
Parallel Load
1
1
16
s0
s1
D
Serial Input
I0
Mode
Register Op.
D
S1
S0
I1
No Change
0
0
Shift right (down)
1
0
D
Shift left (up)
1
0
I2
Parallel Load
1
1
D
Serial Input
I3
Clock
17
Mode
S1
S0
0
0
1
0
1
0
1
1
18
Mode
Register Op.
S1
S0
No Change
0
0
1
0
Shift right (down)
1
0
Shift left (up)
1
1
Parallel Load
19
Mode
Register Op.
S1
S0
No Change
0
0
1
0
Shift right (down)
1
0
Shift left (up)
1
1
Parallel Load
20
Mode
Register Op.
S1
S0
No Change
0
0
1
0
Shift right (down)
1
0
Shift left (up)
Parallel Load
1
1
21
Memory

• A memory unit is a collection of storage cells
  needed to transfer information in and out of
  storage
• Word is the unit of info.
• stored transferred in
• out of memory
• A decoder accepts address
• and opens the path to select
• specified words
• address decoder

Memory
32x232 Decoder
A 32 bit addr. line
232 words
32 bit word