Dataflow Style Combinational Design with VHDL

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Dataflow Style Combinational Design with VHDL

• IAY 0600Digital Systems Design

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Combinational systems

• Combinational systems have no memory. A
  combinational system's outputs are a function of
  only its present input values.
• No latches/FFs or closed feedback loop
• Combinational system description can be in
  dataflow, behavioral, or structioral styles.
• Concurrent signal assignment signal is basic for
  dataflow style combinational design.

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More about architecture body. Coding styles
An architecture body defines either the behavior
or structure of a design entityhow it
accomplishes its function or how it is
constructed. As such, it provides the internal
view of a design entity.
We can have different architectures associated
with the same entity declaration, creating
different design entities.
An architecture can be written in one of three
basic coding styles dataflow, behavioral, or
structural. The distinction between these styles
is based on the type of concurrent statements
used A dataflow architecture uses only
concurrent signal assignment statements. A
behavioral architecture uses only process
statements. A structural architecture uses only
component instantiation statements.
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BIT versus STD_LOGIC

• BIT type can only have a value of 0 or 1
• STD_LOGIC can have nine values
• 'U',0,1,X,Z,W,L,H,-
• Useful mainly for simulation
• 0,1, and Z are synthesizable

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Dataflow style half-adder description
library ieee use ieee.std_logic_1164. all
entity half_adder is port (a, b in
std_logic sum, carry_out out std_logic) end
half_adder
architecture data_flow of half_adder
is begin sum lt a xor b -- concurrent signal
assignment carry_out lt a and b --
concurrent signal assignment end data_flow
Signal assignment statement placed in the
statement part of an architecture is a concurrent
statement.
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Behavioral style half-adder coding
entity half_adder is port (a, b in
std_logic sum, carry out std_logic) end
half_adder architecture behavior of half_adder
is begin ha process (a, b) begin if
a 1 then sum lt not b carry lt b
--sequential signal assignments else
sum lt b carry lt 0 end if end
process ha end behavior
We can have different architectures associated
with the same entity declaration, creating
different design entities.
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Signal assignment statement
Signal assignment statement placed in the
statement part of an architecture is a concurrent
statement.
Concurrent signal assignment statements assigns a
new value to the signal on the left-hand side of
the signal assignment symbol (lt) whenever there
is an event on one of the signals on the
right-hand side of the assignment symbol. The
signal assignment statement is said to be
sensitive to the signals on the right-hand side
of the statement. The symbol lt is read as gets.

• We consider three kinds of concurrent signal
  assignment
• Concurrent signal assignment statement using a
  Boolean expression
• Selected signal assignment statement
• Conditional signal assignment statement

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Concurrent signal assignment with a closed
feedback loop

• Signal assignment statement with a closed
  feedback loop
• a signal appears in both sides of a concurrent
  assignment statement
• For example, q lt ((not q) and (not en)) or (d
  and en)
• Syntactically correct
• But form a closed feedback loop
• Should be avoided

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Concurrent signal assignment using a Boolean
expression (4 bit equality comparator example)
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Concurrent signal assignment using a Boolean
expression (4 bit equality comparator example)
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Concurrent signal assignment using a Boolean
expression (4 bit equality comparator example)
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Type Boolean
The result from evaluating a condition is type
boolean. type boolean is (false, true)
The leftmost literal in an enumeration listing is
in position 0. Each enumeration type definition
defines an ascending range of position numbers.
Example type std_ulogic is ('U', 'X', '0',
'1', 'Z', 'W', 'L', 'H', '-') ' Z ' (with
position number 4) iz greater than ' 1 ' (with
position number 3
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Conditional signal assignment statement(4 bit
equality comparator example)
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4-to-1 multiplexer using a Boolean expression
library ieee use ieee.std_logic_1164.all entity
mux4to1 is port (c3, c2, c1, co in
std_logic g_bar, b, a in std_logic y out
std_logic) end mux4to1 architecture dataflow of
mux4to1 is begin y lt not g_bar and ( (not b and
a and c0) or (not b and a and c1) or (b and not
a and c2) or (b and a and c3)) end dataflow
What is STD_LOGIC?
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Selected signal assignment statement
with select_expression select signal_name
lt value_expr_1 when choice_1, value_expr_2 when
choice_2, value_expr_3 when choice_3, . .
. value_expr_n when choice_n
The value of one and only one choice must equal
the value of the select expression.
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Selected signal assignment statement.Example
mux4to1
library ieee use ieee.std_logic_1164.all entity
mux4to1 is port (c3, c2, c1, c0 in
std_logic g_bar, b, a in std_logic y out
std_logic) end mux4to1 architecture selected of
mux4to1 is begin with std_logic_vector' (g_bar,
b, a) select y lt c0 when "000", c1 when
"001", c2 when "010", c3 when "011" '0' when
others -- default end selected
Here we use an aggregate (g_bar, b, a) in a
select expression
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Type qualification. Choices completeness
We must explicitly specify the aggregat's (g_bar,
b, a) type. This is accomplished using a type
qualification (') std_logic_vector' (g_bar, b,
a).
If we use this aggregate alone, the compiler
cannot tell the aggregates type from the
context. The compiler does not simply assume that
an aggregate of std_logic elements is type
std_logic_vector, since there are other array
types, such as unsigned, that have std_logic
elements (lect. 7)
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Type qualification. Choices completeness
To describe combinational logic, the choices
listed in a selected signal assignment must be
all inclusive. That is, they must include every
possible value of the select expression.
The last clause (default assignment) uses the
keyword others to assign the value of 0 to y for
the 725 values of the select expression not
explicitly listed. 93729, 729-4725
y lt c0 when "000", c1 when "001", c2 when
"010", c3 when "011" '0' when others
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Example mux4to1
library ieee use ieee.std_logic_1164.all
entity mux4to1 is port (c3, c2, c1, co in
std_logic g_bar, b, a in std_logic y out
std_logic) end mux4to1 architecture conditional
of mux4to1 is signal tmp std_logic_vector (2
downto o) begin tmp lt (g_bar, b, a) y lt c0
when tmp "000" else c1 when tmp "001"
else c2 when tmp "010" else c3 when tmp
"011" else '0' -- default assignment end
conditional
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Avoiding implied latches
The last value_expression must not have an
associated when condition clause (default
assignment).
For example, lets take previous description. If
the conditional signal is written as y lt c0
when tmp "000" else c1 when tmp "001"
else c2 when tmp "010" else c3 when tmp
"011" the VHDL interpretation of this
construct is that, for the 4 specified values of
tmp, a new value should be assigned to y. This
implies that for all other values of tmp the y
should retain its previous value. As a result,
the synthesizer generates a latch at the output
of the combinational logic to store the value of
y.
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Synthesised mux logic with undesired latch