FOUR BIT CARRY LOOK AHEAD ADDER

1
FOUR BIT CARRY LOOK AHEAD ADDER

• SUBMITTED BY
• MILAN PATNAIK
• SHANTHI TENNETI
• DURGA L NALLARI
• ADVISOR PROF. DAVID PARENT
• DATE 12-06-2004

2
Agenda

• Abstract
• Introduction
• why
• Theory of operation
• Project (Experimental) Details
• Results
• Cost Analysis
• Conclusions

3
Abstract

• We designed a 4-bit carry look ahead adder that
  operates at 263 MHz and uses 4.37?W (3.06mW/sqcm)
  of Power and occupies an area of 404?m x 353?m

4
Introduction

• Most widely used design for high speed adders.
• - explicit arithmetic operations
• - computing physical addresses in most
• modern CPUs.
• - used in digital systems where full
  fledged
• CPUs are superfluous.
• Speed of various digital systems significantly
  influenced by speed of adders.

5
Theory of operation

• Carry values calculated independently (determines
  carry ahead of time)
• Propagate and Generate terms
• Gi Ai Bi and Pi Ai XOR Bi
• Then outputs can be summarized as,
• SiPi xor Ci Ci1Gi PiCi
• C1Previous carry
• C2 G1 P1C1  
• C3  G2P2G1P2P1C1    
• C4G3P3G2P3P2G1P3P2PC1
• C5G4P4G3P4P3G2P4P3P2C2                       
           

1BIT FULL ADDER
6
Project Details

• Initial hand calculations
• Block level schematics
• Block level layouts
• Total schematic
• Integration of the block level layouts
• Circuit extraction LVS
• Post extraction simulations

7
DESIGN FLOW
8
Cg of Driver MUX (master ff) 19.93fF which
matches the Cg 20fF assumption.
9
Schematic
10
Layout
11
LVS REPORT
12
DFF timings
T hold (rise)0.5n T hold (fall)0.48n T setup
(rise)0.73n T setup (fall)0.64n
13
Test bench
14
Simulation (clock period5n)
15
Simulations
Period 4ns
Period3.5ns
16
Simulation (clock period3.8n)
17
Cost Analysis

• Time spent on the various phases of the project
• verifying logic(2 days)
• Hand calculations(1 week)
• Layout(4 days)
• Modifying layout(2 days)
• post extracted simulations(1 day)

18
Lessons Learned

• Start working as early as possible!!
• Plan the layout beforehand for an efficient
  design.
• Use the same cell heights for all the blocks.

19
Summary

• Our CLA operates at 263 MHz of Clock Frequency,
  uses 4.37?W of Power and occupies an area of
  404?m x 353?m
• The adder can be designed with lesser
• area and power consumption with a more
• organized Layout

20
Acknowledgements

• Thanks to Cadence Design Systems for the VLSI lab
• Thanks to Synopsys for Software donation
• Thanks to Professor David Parent
• Thanks to EE166 Classmates