IC ProcessingTechnology

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IC ProcessingTechnology

• Hacettepe Universitesi
• Elektrik ve Elektronik Mühendisligi Böümü
• Ankara

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Silikon Yapimi
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Silikon olusumu
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Silikondan diea
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Modern MOS tasarim
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MOS üretim kisaca
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MOS Fabrikasyon

• CMOS transistors are fabricated on silicon wafer
• Lithography process similar to printing press
• On each step, different materials are deposited
  or etched

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Photo-Lithographic Süreç
oxidation
Optical mask
stepper exposure
photoresist coating
photoresist
removal (ashing)
Photoresist developmen
acid etch
Process step
spin, rinse, dry
Typical operations in a single photolithographic
cycle (from Fullman).
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Inverter Mask Set

• Transistors and wires are defined by masks
• Cross-section taken along dashed line

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Detailed Mask Views

• Six masks
• n-well
• Polysilicon
• n diffusion
• p diffusion
• Contact
• Metal

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Fabrication Steps

• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
• Cover wafer with protective layer of SiO2 (oxide)
• Remove layer where n-well should be built
• Implant or diffuse n dopants into exposed wafer
• Strip off SiO2

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Oxidation

• Grow SiO2 on top of Si wafer
• 900 1200 C with H2O or O2 in oxidation furnace

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Oxidation
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Photoresist

• Spin on photoresist
• Photoresist is a light-sensitive organic polymer
• Softens where exposed to light

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Lithography

• Expose photoresist through n-well mask
• Strip off exposed photoresist

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Lithography Sequence
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SiO2 sekillendirme
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2
(d) After development and etching of resist,
chemical or plasma etch of SiO
2
Si-substrate
Hardened resist
(b) After oxidation and deposition
SiO
of negative photoresist
2
Si-substrate
UV-light
Patterned
(e) After etching
optical mask
Exposed resist
SiO
2
Si-substrate
Si-substrate
(f) Final result after removal of resist
(c) Stepper exposure
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Etch

• Etch oxide with hydrofluoric acid (HF)
• Seeps through skin and eats bone nasty stuff!!!
• Only attacks oxide where resist has been exposed

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Strip Photoresist

• Strip off remaining photoresist
• Use mixture of acids called piranah etch
• Necessary so resist doesnt melt in next step

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n-well

• n-well is formed with diffusion or ion
  implantation
• Diffusion
• Place wafer in furnace with arsenic gas
• Heat until As atoms diffuse into exposed Si
• Ion Implanatation
• Blast wafer with beam of As ions
• Ions blocked by SiO2, only enter exposed Si

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n-well
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Strip Oxide

• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of steps

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Polysilicon

• Deposit very thin layer of gate oxide
• lt 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon layer
• Place wafer in furnace with Silane gas (SiH4)
• Forms many small crystals called polysilicon
• Heavily doped to be good conductor

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Polysilicon Patterning

• Use same lithography process to pattern
  polysilicon

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Self-Aligned Process

• Use oxide and masking to expose where n dopants
  should be diffused or implanted
• N-diffusion forms nMOS source, drain, and n-well
  contact

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N-diffusion

• Pattern oxide and form n regions
• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned
  gates because it doesnt melt during later
  processing

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N-diffusion cont.

• Historically dopants were diffused
• Usually ion implantation today
• But regions are still called diffusion

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N-diffusion cont.

• Strip off oxide to complete patterning step

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P-Diffusion

• Similar set of steps form p diffusion regions
  for pMOS source and drain and substrate contact

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Channel Stop Implant
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Channeling in Ion Implantation
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Self Aligned Structure
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Back end processing
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Contacts

• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed

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Metallization

• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires

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Active Spiking
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Inverter Cross-section

• Typically use p-type substrate for nMOS
  transistors
• Requires n-well for body of pMOS transistors

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Well and Substrate Taps

• Substrate must be tied to GND and n-well to VDD
• Metal to lightly-doped semiconductor forms poor
  connection called Schottky Diode
• Use heavily doped well and substrate contacts /
  taps

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Layout

• Chips are specified with set of masks
• Minimum dimensions of masks determine transistor
  size (and hence speed, cost, and power)
• Feature size f distance between source and
  drain
• Set by minimum width of polysilicon
• Feature size improves 30 every 3 years or so
• Normalize for feature size when describing design
  rules
• Express rules in terms of l f/2
• E.g. l 0.3 mm in 0.6 mm process

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Simplified CMOS Inverter Process
cut line
p well
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P-Well Mask
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Active Mask
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Poly Mask
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P Select Mask
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N Select Mask
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Contact Mask

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Metal Mask
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Advanced Metallization
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Simplified Design Rules

• Conservative rules to get you started

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Summary

• MOS Transistors are stack of gate, oxide, silicon
• Can be viewed as electrically controlled switches
• Build logic gates out of switches
• Draw masks to specify layout of transistors
• Now you know everything necessary to start
  designing schematics and layout for a simple chip!

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Design Rules
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3D Perspective
Polysilicon
Aluminum
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Design Rules

• Interface between designer and process engineer
• Guidelines for constructing process masks
• Unit dimension Minimum line width
• scalable design rules lambda parameter
• absolute dimensions (micron rules)

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Olasi Hatalar

• Maske hizalama hatasi
• Toz
• Proses parametereleri
• Engebeler

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CMOS Process Layers
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Poly Kontakt Diff Kontakt
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Intra-Layer Design Rules
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Metal2
3
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Inter-Layer Design Rule Origins

• Transistor rules transistor formed by overlap
  of active and poly layers

Transistors
Catastrophic error
Unrelated Poly Diffusion
Thinner diffusion, but still working
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Inter-Layer Design Rule Origins,

• Contact and via rules

M1 contact to p-diffusion
M1 contact to n-diffusion
Contact Mask
M1 contact to poly
Mx contact to My
Via Masks
mask misaligned
0.3
both materials
Contact 0.58 x 0.58
0.14
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Transistor Layout
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Metal baglantilari
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Via metal baglantilar
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Select Layer
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P diff n diff arasi
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CMOS Inverter Layout
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Layout Editor
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Design Rule Checker DRC
poly_not_fet to all_diff minimum spacing 0.14
um.
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Hatali DRC sonuçlari
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Kullanilan yazilim Mentor Graphics IC programi
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Passive Devices

• Resistors

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• -50 variation in value

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Passive Devices

• Capacitors

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Passive Devices
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Capacitor mask necessity
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Issues with poly sub cap
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Simplest capacitor
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Paralel Plate and Fringe Cap
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Latch up
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Antenna Effect
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Analog Layout Techniques
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Folding
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Symmetry
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Symmetry
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Paketleme
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Paketleme Gereksinimleri

• Electrical Low parasitics
• Mechanical Reliable and robust
• Thermal Efficient heat removal
• Economical Cheap

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Bonding - Baglanti Teknikleri
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Tape-Automated Bonding (TAB)
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Flip-Chip Bonding
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Package-to-Board Interconnect
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Package Parameters
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Packages

• Package functions
• Electrical connection of signals and power from
  chip to board
• Little delay or distortion
• Mechanical connection of chip to board
• Removes heat produced on chip
• Protects chip from mechanical damage
• Compatible with thermal expansion
• Inexpensive to manufacture and test

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Package Types
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Package Types

• Through-hole vs. surface mount

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Multichip Modules

• Pentium Pro
• Fast connection of CPU to cache
• Expensive,

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Chip-to-Package Bonding

• Traditionally, chip is surrounded by pad frame
• Metal pads on 100 200 mm pitch
• Gold bond wires attach pads to package
• Lead frame distributes signals in package
• Metal heat spreader helps with cooling

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Heat Dissipation

• 60 W light bulb has surface area of 120 cm2
• Itanium 2 die dissipates 130 W over 4 cm2
• Chips have enormous power densities
• Cooling is a serious challenge
• Package spreads heat to larger surface area
• Heat sinks may increase surface area further
• Fans increase airflow rate over surface area
• Liquid cooling used in extreme cases ()

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Input / Output

• Input/Output System functions
• Communicate between chip and external world
• Drive large capacitance off chip
• Operate at compatible voltage levels
• Provide adequate bandwidth
• Limit slew rates to control di/dt noise
• Protect chip against electrostatic discharge
• Use small number of pins (low cost)

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I/O Pad Design

• Pad types
• VDD / GND
• Output
• Input
• Bidirectional
• Analog

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Output Pads

• Drive large off-chip loads (2 50 pF)
• With suitable rise/fall times
• Requires chain of successively larger buffers
• Guard rings to protect against latchup
• Noise below GND injects charge into substrate
• Large nMOS output transistor
• p inner guard ring
• n outer guard ring
• In n-well

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Input Pads

• Level conversion
• Higher or lower off-chip V
• May need thick oxide gates
• Noise filtering
• Schmitt trigger
• Hysteresis changes VIH, VIL
• Protection against electrostatic discharge

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ESD Protection

• Static electricity builds up on your body
• Shock delivered to a chip can fry thin gates
• Must dissipate this energy in protection circuits
  before it reaches the gates
• ESD protection circuits
• Current limiting resistor
• Diode clamps
• ESD testing
• Human body model
• Views human as charged capacitor

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Bidirectional Pads

• Combine input and output pad
• Need tristate driver on output
• Use enable signal to set direction
• Optimized tristate avoids huge series transistors

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Analog Pads

• Pass analog voltages directly in or out of chip
• No buffering
• Protection circuits must not distort voltages

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MOSIS I/O Pad

• 1.6 mm two-metal process
• Protection resistors
• Protection diodes
• Guard rings
• Field oxide clamps

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Multi-Chip Modules