Processor Types And Instruction Sets

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Processor Types And Instruction Sets

• Barak Perelman
• CS147 Prof. Lee

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ISA

• Instruction Set Architecture
• All programmer accessible hardware instructions
  for that hardware

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System as Whole

• CPU (Central Processing unit) interaction with
  main memory (its internal memory)
• Input Output

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System Bus

• CPU connected with main memory I/O via System
  Bus
• CPU generates addresses placed on Address bus
• Memory receives addresses from Address bus
• THIS PROCESS NEVER REVERSED

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CPU Memory

• Since CPU executes instructions, and all
  instructions/data stored in Memory.
  Instructions/data must be loaded to CPU
  registers, and results stored back in Memory.

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A Bit about Memory (no pun intended)

• Memory is a collection of consecutive cells 1
  byte (8 bits)
• Each cell has address/memory location
• Group of cells WORD usually 4 Bytes
• Convention WORD accessed by referencing byte
  with lowest byte
• Computers memory is an array of bytes

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CPU 2 Sections

• 1. Data Section Registers ALU
• 2. Control Section interprets instructions and
  controls register transfers executes
  instructions stored in main memory

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Interface between Data and Control Units

• Register 1 Program Counter (PC) or IP
  (Instruction Pointer in IA) address of
  instruction executed
• Register 2 Instruction register (IR) fetched
  instruction (PC pointed) stored in IR and
  interpreted

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FETCH-EXECUTE CYCLE

1. Fetch next instruc. To be exec. from memory
2. Decode operation code
3. Read operand(s) from main memory if any
4. Exec. Instruc. and store results if any
5. Go step 1

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Control unit Data unit (datapath) again

• Control unit decodes instruction after fetch,
  and performs specific action. Coordinates this
  in execution of program.
• Datapath Collection of registers (register
  file) , arithmetic and logic unit, and other
  registers.

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Datapath - gt Register file

• Register file used like temporary memory
  during computation.
• Can be many register files (depend on CPU). Each
  has own address (in sequence, like main memory,
  but with much smaller addresses ex 32 register
  file uses 5-bit address).
• Register file in CPU (much faster than system
  memory 10Xs-100Xs)

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ALU

• Implements variety binary (2-operand) and unary
  (one-operand) operations (ex add, and, not, or,
  multiply)

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The Process

• Control Unit selects operandsoperations
  according to executable instruction
• The two source operands fetched from register
  file onto Register Source Buses to ALU
• Output from ALU goes on Register Destination Bus,
  back to register file
• Most systems include System Bus in this process
  (access memory and devices)

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Instruction Set

• Collection of instructions that a processor can
  execute lt-therefore defining the processor

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3 Types of Instructions

1. Data move data between CPU and memory or I/O
2. Arithmetic (logic) arithmetic logic
   operations on data
3. Control transfer control from one section to
   another

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Problems

• Incompatibility of instruction sets
• Solutions
• Higher-level languages recompiled for target
  processor

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Exception

• JAVA byte code actual machine language for
  virtual machine. Therefore will run on any
  processor running JVM (Java Virtual Machine)

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CPU types

• IBM PC (or compatible) use instruction set 80x86
  CPU (where x replaced w/digit of version.
  Example 80586 aka Pentium processor) (also need
  to consider differences in in operating systems
  and I/O)
• Sun Microsystem SPARC
• Motorola