CSL718 : Multiprocessors

1
CSL718 Multiprocessors

• Interconnection Mechanisms
• Performance Models
• 20th April, 2006

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Connecting Processors and Memories

• Shared Buses
• Interconnection Networks
• Static Networks
• Dynamic Networks

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Shared Bus
each processor sees this picture
processing
bus access
prob of a processor using the bus ? prob of a
processor not using the bus 1 ? prob of none
of the n processors using the bus (1 ?)n prob
of at least one processor using the bus 1 (1
?)n achieved BW on a relative scale 1 (1
?)n required BW n ? available BW 1
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Effect of re-submitted requests
? (1-PA )
1- ? ?PA
1-PA
A
W
PA
prob qA
prob qW
5
(No Transcript)
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(No Transcript)
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Waiting time
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Switched Networks

• BUS
• Shared media
• Lower Cost
• Lower throughput
• Scalability poor

• Switched Network
• Switched paths
• Higher cost
• Higher throughput
• Scalability better

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Interconnection Networks

• Topology who is connected to whom
• Direct / Indirect where is switching done
• Static / Dynamic when is switching done
• Circuit switching / packet switching how are
  connections established
• Store forward / worm hole routing how is the
  path determined
• Centralized / distributed how is switching
  controlled
• Synchronous/asynchronous mode of operation

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Direct and Indirect Networks
link
node
node
P M S
node
P M S
link
node
SWITCH
link
link
link
link
link
node
node
S M P
node
S M P
link
node
DIRECT
INDIRECT
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Static and Dynamic Networks

• Static Networks
• fixed point to point connections
• usually direct
• each node pair may not have a direct connection
• routing through nodes
• Dynamic Networks
• connections established as per need
• usually indirect
• path can be established between any pair of nodes
• routing through switches

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Static Network Topologies
Non-uniform connectivity
2D-Mesh
Linear
Tree
Star
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Static Networks Topologies- contd.
Uniform connectivity
Ring
Torus
Fully Connected
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Illiac IV Mesh Network
0
0
1
2
1
8
3
4
5
2
7
6
7
8
3
6
4
5
neighbors of node r (r ? 1) mod 9 and (r ? 3)
mod 9
Chordal Ring
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Fat Tree Network
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Dynamic Networks
k ? k cross -bar switch
building block for multi-stage dynamic networks
simplest cross-bar
2 ? 2 switch
straight
exchange
upper broadcast
lower broadcast
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Baseline Network
000
000
001
001
010
010
011
011
100
100
101
101
110
110
111
111
blocking can occur
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Benes Network
non-blocking
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Switching Mechanism

• Circuit Switching (connection oriented
  communication)
• A circuit is established between the source and
  the destination
• Packet Switching (connectionless communication)
• Information is divided into packets and each
  packet is sent independently from node to node

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Routing in Networks
node
outgoing message
incoming message
header payload/data
store forward routing
time
worm hole routing
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Routing in presence of congestion

• Worm hole routing
• When message header is blocked, many links get
  blocked with the message
• Solution cut-through routing
• When message header is blocked, tail is allowed
  to move, compressing the message into a single
  node

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Routing Options

• Deterministic routing always same path followed
• Adaptive routing best path selected to minimize
  congestion
• Source based routing message specifies path to
  destination
• Destination based routing message specifies only
  destination address

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Some Performance Parameters
overhead
Tx timebytes/BW
sender
time of flight
overhead
Tx timebytes/BW
receiver
transport latency
total latency
time
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Other Parameters

• Throughput ? Bandwidth (no credit for header)
• Bisection bandwidth BW across a bisection
• Node degree
• Network Diameter
• Cost
• Fault Tolerance

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Multidimensional Grid/Mesh

• Size
• k ? k ? . ? k (n times)
• k n
• Diameter
• (k-1) ? n without end around
• connections
• k ? n /2 with end around
• connections

k-ary n-cube
for (Binary) Hypercube k 2
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Grid/Mesh Performance - 1
kd
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Grid/Mesh Performance - 2
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Grid/Mesh Performance - 3
k-ary n-cube
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Switch Performance
k ? m cross -bar switch
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Switch Performance contd.
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Switch Performance contd.
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Effect of re-submitted requests
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Effect of buffering

• There are two possibilities
• Buffering before switching (k buffers, one at
  each input port)
• Buffering after switching (m buffers, one at each
  output port)

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Switch with input buffers

• Rate of messages at input and output of each
  queue is same in steady state - r per cycle
• Service time includes delays due to conflicts,
  calculated as earlier. This has an
  exponential distribution recall the analysis
  for a shared bus.
• M/M/1 open queue model can be used to calculate
  queuing delay. Details are omitted.

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Switch with output buffers

• Here we assume that all the messages destined for
  same output are queued in the same buffer, in
  some order. That is no rejections and no
  re-submissions.
• For each queue,
• Messages arriving per service cycle ?
• Prob of a request coming from one of
• the k sources p
• Apply MB/D/1 model for finding queuing delay Tw

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References

• D. Sima, T. Fountain, P. Kacsuk, "Advanced
  Computer Architectures A Design Space
  Approach", Addison Wesley, 1997.
• K. Hwang, "Advanced Computer Architecture
  Parallelism, Scalability, Programmability",
  McGraw Hill, 1993.