CPLD

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CPLD
MaxplusII
? ? ? ? ? ?
Design by ??? ??
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? ?
??? ??(??????)----------P5 1???????
2????? 3????? ??(CPLD????)---------P12
1???CPLD 2???CPLD????? ?? (?????????)---P16
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??(VHDL??????) -----P20 1??????VHDL??
2?VHDL????????? 3?????Mapping
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???
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????????
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????????
1????? ????????????,????????????????????
??????????,?????????????,??????????,???????????
?????????????????????,??????,?????????,??????,????
??0???1????
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????,?????????????,???????????,???????????????
??????,?????????????????????????????????,????
???????,??????,??????????,??????????,?????????????
????????????????,????????????,???????
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2????? ??????,??????????,????(AND)???(OR)??
?(NOT)?????(XOR)???,???????(??)??,???????(??),????
????????
(??)
(??)
(??)
(????)
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???????
1???
YAB
2???
YAB
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???????
3?????
YA B
4???
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3????? ?????????????,???????????????????????
,???????,????????????,???????,???????,????????????
???????,????????????????,?????????????????????????
?????,????????????????????????,???????????????????
????? ???????????????,??????(Flip-Flop)??
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??CPLD ????
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??CPLD ????
1???CPLD ??????????,?????????????????????
?????????????????????????,??????????????????,?????
??????,??????????????,??????????
?????????????????,??????????????????????,?????????
?????????????????????
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???????,?????????????????,????????,???????
????,?????????,????????????????????
?????????????????,???????????????,????????????????
??,?????????????,?????????(EDA)?????,?????????????
??????????????,??????????????????????
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?PLD(Programmable Logic Device)
????????????????????????????????(PLD)?????????????
????????(Standard Logic)???????(ASIC)???PLD?ASIC?
??? PLD????????????/???PLD(Simple
PLD)????PLD(Complex PLD)?????????(FPGA)?
????????PLD??,?????? CPLD?????,??????
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?????? ? ????
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???????(?)
?????????????????? ????????????????????
????????????????? SSI (Small
Scale Integrated Circuit) ?????????????????????
??,?????? Decoder ???? ?
Demultiplexer ???? Multiplexer ? ???
Adder ???? Flip Flop ?? ????Shift
Register ????Counter ???????
MSI(Medium Scale
Integrated Circuit)
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???????? MSI ????????? ??????? LSI
?VLSI ? ?????????????,??????
???????????????? ????????????????
????(??????)????? ?????????????,??
?????????????,??
??????????(Programmable
Logic Device) PLD???????? ?(Filed
Programmavle Gate Array) FPGA
????(Micro Controller) ????? (Micro
Processor)????????ASIC
(Application Specific Integrated Circuit) ?
????????
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??VHDL??????
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???? VHDL ?????????
Library ??
USE ??
PACKAGE ??
Entity ??
Architecture ??????? . . . Begin DataFlow
?? Behavior ?? Structure ?? end
Configuration??
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Architecture ?
??????
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??????? (Architecture Describe)
VHDL ????????? ???????? ( Data Flow
Description) ?????????????????Assignmen
t ?????????????????,????????? VHDL
???????????? 1????????? lt 2????
conditional ????? when else 3???? Selected
????? with select when
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??? ?????(Behavior Description) ,????????
process?????????????????Behavior Model
????????????????,?process ???????????????
Sequential??,?????????????,????????????,??????????
?????????????? process ?????????????,?????
Architecture ???,???????? Label
process ( Sensitivity List )
Declaration area
begin
Behavior statement end
process Label
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IF T HEN END IF if then endif
???????????????( ????? ELSE ?? ) ,??????
if ?? then ??? end if
??? if then endif ??????????? D
???? ?????? Architecture ??? if
( CK event ) and ( CK 1 ) then
Q lt D end
if
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IF T HEN ELSE END IF if then
else end if ??????????????( ????? ELSE ??
) ,?????? if ?? then ???
T else ??? F end if
??? if then else end if
????????? ?????? Architecture ???
if A B then F lt
1 then
F lt 0 end if
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??? ?????? (Structure Description)
,???? ??????????????????????? ,???????????????????
??? ????????????Component? ???????????????????? ?
??(Hierarcky)?????????????? ????????????(??),?????
?? ????????,?????????????? ???????????????????????
??????????????????????? ???,????????????,?????
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1????????Component Declaration? 2??????????Mapping
? ????Component Declaration Component
Component_name port ( Signal_name 1 mode Data
type Signal_name 2 mode Data
type Signal_name n mode Data
type ) end Component
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????Mapping???????,????
??? ??????Mapping By name LABEL1
Component_name port map( Signal_name 1 gt
Signal_name 1, Signal_name 2 gt Signal_name
2, Signal_name n gt Signal_name
n, ) end Component
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1?LABEL ?????? 2?Component_name????????,
? ??????????? 3?port map(
)????????????
?????????????????
???????,????????? ???,?????????????
,??? gt ?????
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??????Mapping By position
Label1Component_name port map ( Signal1,
Signal2,,Signal n )
1?LABEL ?????? 2?Component_name????????,?
??????????? 3?port map(
)????????????
?????????????????
?port???????????,??? ???,???????????
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???????(?)
1?SSI(Small Scale Integrated
Circuit) ??????????,?????, ??????????????
??????????????? ?,?NOT?AND?OR?NOR?
???????SSI?
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• 1-1
• ?SSI(??SN74XX???
• SN54XX???)
• ?????????? IC,??
• SN7404 ? SN7408??
• SN7432????????
• ???,????????
• ????????????
• ????????????
• ???,?????????

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2?MSI(Medium Scale Integrated
Circuit) ???????????????? ???(Karnaugh-Map)??
?, ?????? Decoder ???? ??( De-mulplexer
)???? ??( Shift Register )????
??(counter)???????, ?????MSI?
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• 2-1
• ? MSI?SSI??????????
• ,?????????,??
• ??????? Minterm
• ??? OR ???????
• ??,?????????
• ??????Minterm??
• ????,???????
• ??,????? ??? ?
• ????OR???????,
• ??????MSI?

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3?LSI(Large Scale Integrated
Circuit) ?? ?????,????MSI?????
???????????????, LSI?VLSI?????????
????,?????????? ????????,?????? ??PLD????
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3-1 ? LSI??MSI???,?????
????????????? ???????,?????
?,???????LSI?? ?VLSI,?????PLD?
?,?PROM?PLA?PAL?
GAL?PEEL?FPGA???, ?????????????
????,????????, ?????????????
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4?PLD(Programmable Logic Device)
?? ?????????????????, ???????????PLD???
???????FPGA????MC? ????MP??????IC,?? ???????
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• 4-1
• ?PLD(PROM?PLA?PAL?FPGA)
• ? PROM?????????PROM
• ?????? PLD ??,
• ????????????
• ???,??????ROM
• ???????? (?NOT
• ?AND??????,??
• ?AND?????????
• ?????Minterm ),??
• ????????OR???

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• 4-2
• ?PLD(PROM?PLA?PAL?FPGA)
• ? PLA????????PLA
• (Programmable Logic Array)??
• ????PROM??,?
• ????????PLA?
• AND ?? OR ??????
• ????????????
• ????????????
• ?,??????PROM
• ????

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• 4-3
• ?PLD(PROM?PLA?PAL?FPGA)
• ? PAL????????PLA
• (Programmable Array Logic)??
• ???? PROM? PLA?
• ?,??????PAL??
• AND ?????,?O R ?
• ????????PAL??
• ????,?????PLD
• ??????,?????
• ????????

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• 4-4
• ?PLD(PROM?PLA?PAL?FPGA)
• ?PEEL????????????
• ???PEEL (Programmable
• Electrically Erasable Array
  Logic)
• ??????PAL??,?
• ??????AND ?? OR
• ????????OR???
• ????????MACRO
• CELL ?????????
• ??????????

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• ?????????FPGA
• (Field Programmable GateArray)
• ????????????
• ?,???PEEL????
• ???????,?FPGA
• ???????????,
• ???????????
• FPGA ????????IC
• ????????????

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• 4-5
• ?PLD(PROM?PLA?PAL?FPGA)
• ?FPGA?????,??????
• ???CLB (Configurable Logic
• Block) ,IC???CLB???
• ????????????
• ??????????CLB
• ???????,????
• ?????????- ??
• ???IOB,??????
• ??????

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??? ???-------?? ???-------CPLD?????? ???-------C
PLD???????? ???-------CPLD????????? ???-------CPLD
??????
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???---??
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??CPLD?????
a?????? ???????????,??????
??(?????P38-P45)? b?????? ???????P7-P36???? c?
?????,??????(HDL) CPLD??????AHDL?VHDL?
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AHDLVHDL(????)
? AHDL???? SUBDESIGN __design_name (
_input_name INPUT _output_name
OUTPUT ) BEGIN logic
describe END
??? SUBDESIGN ???
??? LOGIC ???
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??1 SUBDESIGN TEST1 ( A , B
INPUT Y OUTPUT )
BEGIN --?? A ? B ?????
Y AB ??????????? END
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??? 1??????? 2??????? 3???????LU 4???????
--??? 5??????? 6????????? 7?BCD????????? 8????(Fli
p-Flop) 9??????????????? 10?????????????
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GDF(???) ? AHDL(???????)
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GDF(???)
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???
?????
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???
????????
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???
??????(LU)
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???
??????--???
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???
??????
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A H D L (??????)
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???
????????
SUBDESIGN Unit6 ( a7..0,b7..0,s2
..0 INPUtT d OUTPUT
) BEGIN CASE s IS WHEN
0gt dab
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WHEN 1gt
dab WHEN 2gt
dab WHEN 3gt
dab WHEN 4gt
dab WHEN 5gt
dab WHEN 6gt
dab WHEN 7gt
dab WHEN OTHERSgt
da END CASE END
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???
BCD?????????
SUBDESIGN Unit7 ( i3..0
INPUtT a,b,c,d,e,f,g
OUTPUT ) BEGIN
???????????
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TABLE i3..0 gt a,b,c,d,e,f,g
H0 gt 1,1,1,1,1,1,0 H1 gt
1,1,1,1,1,1,0 H2 gt 1,1,1,1,1,1,0
H3 gt 1,1,1,1,1,1,0 H4
gt 1,1,1,1,1,1,0 H5 gt
1,1,1,1,1,1,0 H6 gt 1,1,1,1,1,1,0
H7 gt 1,1,1,1,1,1,0 H8
gt 1,1,1,1,1,1,0 H9 gt
1,1,1,1,1,1,0 HA gt 1,1,1,1,1,1,0
HB gt 1,1,1,1,1,1,0 HC
gt 1,1,1,1,1,1,0 HD gt
1,1,1,1,1,1,0 HE gt 1,1,1,1,1,1,0
HF gt 1,1,1,1,1,1,0 END
TABLE END
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???
???
SUBDESIGN Unit8 ( S,R,CLK,PRN,CLRN
INPUtT Q,/Q OUTPUT
) VARIABLE ff srff
BEGIN ff.s ff.r ff.clk ff.prn
Qff.q /Q!ff.q END
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???
??????????????
FUNCTION 7segd (x3..0) RETURNS (s6..0)
SUBDESIGN Unit9 ( clk,load,d7..0
INPUtT dpl6..0,dp26..0
OUTPUT ) VARIABLE ff7..0
DFFE sd1,sd2 7segd
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???????????? BEGIN ff.clk
clk ff.ena load ff.d
d sd1.x ff7..4.q sd2.x
ff3..0.q dp1 sd1.s dp2
sd2.s END
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???
????????????
FUNCTION 7segd (x3..0) RETURNS (s6..0)
SUBDESIGN Unit10 ( clk,en,rst
INPUtT dpl6..0,q4..1
OUTPUT ) VARIABLE ff4..1 TFF
sd1 7segd
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???????????? BEGIN q
ff.q ff.t en ff.clrn
rst ff1.clk clk ff2.clk
ff1.q ff3.clk ff2.q ff4.clk
ff3.q sd1.x ff.q dp1 sd1.s
END
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THE END
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??????
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? ? ? ? ? ?
CPLD
? ? ? ? ? ?
?
?
?
?
?
?
?
?
?? ?? ?? ?? ?? ????
MaxplusII
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????
(??????????????)
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??(??)??
??(??)
(??????????????)