SRAM

1
SRAM DRAM
2
Read-Write Memories (RAM)
3
6-transistor CMOS SRAM Cell
4
CMOS SRAM Analysis (Write)
5
CMOS SRAM Analysis (Read)
6
1-Transistor DRAM Cell
7
DRAM Cell Observations
8
1-T DRAM Cell
9
Advanced 1T DRAM Cells
Word line
Capacitor dielectric layer
Cell plate
Insulating Layer
Cell Plate Si
Isolation
Transfer gate
Capacitor Insulator
Refilling Poly
Storage electrode
Storage Node Poly
Si Substrate
2nd Field Oxide
Trench Cell
Stacked-capacitor Cell
10
Periphery
11
Row Decoders
Collection of 2M complex logic gates Organized in
regular and dense fashion
(N)AND Decoder
NOR Decoder
12
Dynamic Decoders
13
4 input pass-transistor based column decoder
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4-to-1 tree based column decoder
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Sense Amplifiers
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Differential Sensing - SRAM
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Latch-Based Sense Amplifier
18
Open bitline architecture
19
DRAM Read Process with Dummy Cell
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Open Bit-line Architecture Cross Coupling
21
Alpha-particles
22
Yield
Yield curves at different stages of process
maturity (from Veendrick92)
23
Redundancy
24
Redundancy and Error Correction