Design of Regular Quantum Circuits

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Design of Regular Quantum Circuits
Regular circuit tile-based circuit
2

• REVERSIBLE LOGIC

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Reversible Permutative logic Gates and Circuits

• A logic gate is reversible if
• Each input is mapped to a unique output
• It permutes the set of input values
• A combinational logic circuit is reversible if it
  satisfies the following
• Has only one Fanout,
• Uses only reversible gates,
• No feedback path,
• has as many input wires as output wires, and
  permutes the input values.

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Basic Reversible Gates
NOT gate
Controlled-NOT or Feynman gate
a b a c 0 0 0 0 0 1 0 1 1 0 1 1 1 1
1 0
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Basic Reversible Gates
Toffoli gate (Controlled-Controlled NOT gate)
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Basic Reversible Gates
Swap gate
Implementation of Swap gate using controlled-NOT
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Basic Reversible Gates
Fredkin gate (Controlled SWAP gate)
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Algorithms for Synthesis of Reversible Logic
Circuits
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Popular Algorithms for Synthesis of Reversible
Logic Circuits

• MMD Transformation based
• Gupta-Agrawal-Jha PPRM based
• Mishchenko-Perkowski Reversible wave cascade
• Kerntopf Heuristics based
• Wille BDD based synthesis

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reed-mulLER EXPANSION IN SYNTHESIS OF REVERSIBLE
CIRCUITS
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IDEA use reed-mulLER EXPANSION IN SYNTHESIS OF
REVERSIBLE CIRCUITS

• A New Representation is Reed-Muller Expansion
  (Positive Polarity Reed-Muller).
• This idea appeared for the first time in paper of
  Aggrawal and Jha, this paper was a competitor to
  MMD algorithm.
• Now we design a new algorithm which takes into
  account multi-level expansion for reversible
  circuits.

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Example of Agrawal-Jha Algorithm
c b a co bo ao
0 0 0 0 0 1
0 0 1 0 0 0
0 1 0 1 1 1
0 1 1 0 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 1 0 1
1 1 1 1 1 0

• PPRM form for each output in terms of
• Input variables are given as follows and
• node is created

• Reversible function specification is given as a
  truth table shown here
• Output c0, b0 and a0 are derived using EXORCISM-2
  developed at PSU and parent node is created

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Agrawal-Jha Algorithm (cont..)

• Parent node is explored by examining each output
  variable in the PPRM expansion.
• Factors are searched in the PPRM expansions that
  do not contain the same input variable.
• For example in the expansion below appropriate
  terms are c and ac
• The substitution is performed as
• In this example OR

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Agrawal-Jha Algorithm (cont..)
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Agrawal-Jha Algorithm (cont..)
New nodes are created based on substitution
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Next stage of Aggrawal-Jha algorithm
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Next stage of Aggrawal-Jha algorithm
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Solution found by the Aggrawal-Jha algorithm
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Problem with Current Synthesis Approaches

• Common problem with current approaches they
  invariably use nxn Toffoli gates, that might
  imposes technological limitations.
• High Quantum cost of Toffoli gates with many
  inputs.
• Synthesize only reversible functions, not Boolean
  functions that is not reversible.

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Quantum Cost of 4x4 Toffoli Gate

• Implementation of 4x4 Toffoli gate with Quantum
  realizable 2x2 primitives such as controlled-V,
  controlled-NOT, controlled-V.

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• CREATING QUANTUM ARRAY FROM LATTICE

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Expansions Rules for Lattice DIAGRAAMS

• Positive Davio Tree can be created by expanding
  PPRM function using positive Davio expansion.
• Positive Davio Lattice is created by performing
  joining operation for neighboring cells at every
  level.
• Other Lattices can be created using similar
  method but using expansions such as Shannon or
  Negative Davio expansions or combination of them.

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Creating Quantum Array from Lattices

• On the previous foils I showed representation of
  the Davio and Shannon cells as cascade of
  reversible gates.
• Next I present unique method to create Quantum
  Array from Positive Davio Lattice.
• The same approach can be used for other Lattices.

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Creating Positive Davio Lattice

• Each node represents pDv cell.

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Creating Quantum Array from Positive Davio Lattice

c
1


1
d
d
1


1
1
b
b



1
a
1
1
a
1
1
a
1

1
1
d
1
0
1
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Quantum Array Representation
a
b
c
d
garbage
d
0
garbage
1
garbage
1
garbage
1
garbage
a
0
1
function
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Quantum Array Representation
a
b
c
d
garbage
d
0
garbage
1
garbage
1
garbage
1
garbage
a
0
1
function
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Creating Positive Davio Lattice

• Each node represents pDv cell.

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Quantum Array Representation
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Advantages of Lattice to QA

• Reversible circuit synthesized with only 3x3
  Toffoli gates.
• Generates reversible circuit for any ESOP.
• Adds ancilla bits but overall cost of the circuit
  will be lower due to use of low cost 3x3 Toffoli
  gates.

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Calculating Single-Output Shannon Lattice for
Completely Specified Boolean Function.
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Calculating Multi-Output Shannon Lattice for
Completely Specified Boolean Function.
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Calculating Multi-Output Shannon Lattice for
Completely Specified Boolean Function.
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• DIPAL GATES, DIPAL GATE FAMILIES AND THEIR ARRAYS

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Representation of pdv cell as a toffoli gate
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Development of Dipal gate

• Dipal gate is a reversible
• equivalent of Shannon cell

• There are 23! 8! 40320 3x3 Reversible logic
  functions, however only handful of
• them shown earlier are useful for synthesis
  purpose.

• Find the reversible counterpart of well-known
  structures BDD, Lattices, KFDD
• Show Dipal cell is between Toffoli and Fredkin

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Development of Dipal gate (cont..)
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Development of Dipal gate

• Dipal gate is a reversible
• equivalent of Shannon cell

• There are 23! 8! 40320 3x3 Reversible logic
  functions, however only handful of
• them shown earlier are useful for synthesis
  purpose.

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Dipal gate truth table
c b a a
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 1 1 0
0 1 1 1 0 1
1 0 0 1 0 0
1 0 1 1 1 1
1 1 0 0 1 0
1 1 1 0 1 1
input output
0 0
1 1
2 6
3 5
4 4
5 7
6 2
7 3
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Dipal gate unitary matrix
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Variants of Dipal gates
This is called a Dipal Gate Family
General view of Dipal Family Gate
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• EXPERIMENTAL RESULTS

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Results with Pdv Lattice and comparison with MMD
and AJ results
Benchmark Real inputs Garbage inputs Gates Lattice Cost Lattice CPU time Lattice Gates DMM Cost DMM Gates AJ Cost AJ
2to5 5 4 31 107 0.12 15 107 20 100
rd32 3 1 4 8 lt 0.01 4 8 4 8
rd53 5 5 11 39 lt 0.01 16 75 13 116
3_17 3 1 10 21 lt 0.01 6 12 6 14
6sym 10 6 34 150 0.37 20 62 NA NA
5mod5 5 1 14 58 lt 0.01 10 90 11 91
4mod5 4 1 6 18 lt 0.01 5 13 5 13
ham3 3 0 3 7 lt 0.01 5 7 5 9
xor5 5 0 4 4 lt 0.01 4 4 4 4
Xnor5 5 1 5 5 lt 0.01 -------- ---------- ---------- ----------
decod24 4 2 10 30 lt 0.01 -------- ---------- 11 31
Cycle10_2 12 6 180 860 27.9 19 1198 ---------- ----------
ham7 7 5 22 58 0.10 23 81 24 68
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Results with Pdv Lattice and comparison with MMD
and AJ results (cont..)
Benchmark Real inputs Garbage inputs Gates Lattice Cost Lattice CPU time Lattice Gates DMM Cost DMM Gates AJ Cost AJ
graycode6 6 5 5 5 lt 0.01 5 5 5 5
graycode10 10 9 9 9 lt 0.01 9 9 9 9
graycode20 20 19 19 19 lt 0.01 19 19 19 19
nth_prime3_inc 3 4 4 6 lt 0.01 4 6 ---------- ----------
nth_prime4_inc 4 5 16 48 lt 0.01 12 58 ---------- ----------
nth_prime5_inc 5 5 29 91 0.22 26 78 ---------- ----------
alu 5 2 5 17 lt 0.01 -------- ---------- 18 114
4_49 4 4 16 52 0.04 16 58 13 61
hwb4 4 4 12 28 lt 0.01 17 63 15 35
hwb5 5 5 24 96 1.2 24 104 ---------- ----------
hwb6 6 6 32 128 2.0 42 140 ---------- ----------
pprm1 4 4 9 33 lt 0.01 -------- ---------- ---------- ----------
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Results with shannon Lattice
Benchmark Inputs Gates pDv Lattice Cost pDv Lattice Gates Shannon Lattice Cost Shannon Lattice
2to5 5 31 107 41 117
rd32 3 4 8 4 8
rd53 5 11 39 18 46
3_17 3 10 21 15 26
6sym 10 34 150 51 167
5mod5 5 14 58 30 81
4mod5 4 6 18 12 24
Ham3 3 3 7 6 10
xor5 5 4 4 4 4
Xnor5 5 5 5 5 5
Decod24 4 10 30 20 40
Cycle10_2 12 180 860 270 950
Ham7 7 22 58 32 68
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Results with shannon Lattice (cont..)
Benchmark Inputs Gates pDv Lattice Cost pDv Lattice Gates Shannon Lattice Cost Shannon Lattice
Graycode6 6 5 5 5 5
Graycode10 10 9 9 9 9
Graycode20 20 19 19 19 19
nth_prime3_inc 3 4 6 6 8
nth_prime4_inc 4 16 48 29 61
nth_prime5_inc 5 29 91 39 101
Alu 5 5 17 10 22
4_49 4 16 52 22 58
Hwb4 4 12 28 15 31
Hwb5 5 24 96 38 110
Hwb6 6 32 128 40 134
Pprm1 4 9 33 14 38
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• Fig. 2. Circuit for function FX2 created with our
  method for traditional cost function calculation
  that does not take Ion Trap technology
  constraints into account.

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Nearest Linear Node Model
All gates are realized only on neighbors, but we
have to add many SWAP gates

• Fig. 3. Circuit from Figure 2 modified with
  adding SWAP gates for new cost function
  calculation that does take Ion Trap technology
  constraints into account, with XX gates added. It
  has 36 SWAP gates added to realize LNNM.

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Example of Positive Davio Lattice from
Perkowski97d. Positive Davio Expansion is
applied in each node. Variable d is repeated
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Transformation of function F3(a,b,c) from
classical Positive Davio Lattice to a Quantum
Array with Toffoli and SWAP gates. Each SWAP gate
is next replaced with 3 Feynman gates.(a)
intermediate form, (b) final Quantum Array.
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Intermediate Structure with Dipal Gate
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Another Representation of Quantum Array with
Dipal Gate
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Layered Diagram using Dipal Gate

• General layout of the layered diagram
• Each box represents a gate from family of Dipal
  gate

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General Pattern of Circuit with Dipal Gate
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Quantum cost based On 1d model
Benchmark Gates Lattice Cost Lattice Gates with SWAP insertion for Lattice Cost with SWAP gates for Lattice Gates DMM Cost DMM Gates with SWAP insertion for MMD Cost with SWAP gates for MMD
2to5 31 107 61 197 15 107 31 155
rd32 4 8 8 20 4 8 6 14
rd53 11 39 44 138 16 75 72 273
3_17 10 21 14 33 6 12 8 18
6sym 34 150 56 216 20 62 78 236
5mod5 14 58 17 67 10 90 48 204
4mod5 6 18 10 30 5 13 11 31
Ham3 3 7 3 7 5 7 7 13
Xor5 4 4 4 4 4 4 4 4
Xnor5 5 5 5 5 -------- -------- -------- --------
decod24 10 30 14 42 -------- -------- -------- --------
Cycle10_2 180 860 306 1238 19 1198 199 1738
Ham7 22 58 30 112 23 81 79 249
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Quantum cost based On 1d model
Benchmark Gates Lattice Cost Lattice Gates with SWAP insertion for Lattice Cost with SWAP gates for Lattice Gates DMM Cost DMM Gates with SWAP insertion for MMD Cost with SWAP gates for MMD
Graycode6 5 5 5 5 5 5 5 5
Graycode10 9 9 9 9 9 9 9 9
Graycode20 19 19 19 19 19 19 19 19
Nth_prime3_inc 4 6 5 9 4 6 6 12
Nth_prime4_inc 16 48 20 60 12 58 18 76
Nth_prime5_inc 29 91 39 121 26 78 128 384
Alu 5 17 7 23 -------- -------- ---------- ----------
4_49 16 52 41 127 16 58 40 130
hwb4 12 28 15 40 17 63 39 129
hwb5 24 96 44 156 24 104 64 224
hwb6 32 128 72 248 42 140 144 446
pprm1 9 33 19 63 -------- -------- ---------- ----------
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• GENERALIZED REGULARITIES FOR QUANTUM AND
  NANO-TECHNOLOGIES

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Ion-Trap Layout
Interaction between two ions
(
a
)
(
b
)
(
c
)
Single ion
Various regular structures are technically
possible, single dimensional vector is the one
that is most often discussed
(
d
)
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Examples of Expansions for regular structures
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Non-symmetric functions require repeatition of
input variables

• Variable b is repeated

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Symmetry Indices and regular structures for
binary logic
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Example Multi-Valued Reversible Logic Adder
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Multi-Valued Reversible Logic
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Three dimensional realization of lattices for
ternary logic SUM
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Three dimensional realization of lattices for
ternary logic CARRY
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• QUANTUM CIRCUITS AND QUANTUM ARRAYS FROM TRULY
  QUANTUM GATES

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Binary Reversible Gates

• Basic single qubit quantum gates

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• The transformations of blocks of quantum gates to
  the pulses level.

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• Transformation of the circuit realized in Fig. 7
  using Toffoli gate. Each Toffoli and SWAP gates
  are replaced by quantum CNOT and CV/CV quantum
  gates and rearranged to satisfy the neighborhood
  requirements of Ion trap.
•  

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• Lattice based FPGA in CLASSICAL LOGIC

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New type of FPGA in CMOS

• In classical CMOS logic one can design a regular
  array, such as a form of FPGA, which realizes
  Shannon, positive Davio and negative Davio inside
  one cell.
• Such array is highly testable
• We can try to design something similar in quantum
  and reversible logic circuits.

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Design of SRFPGA cell

1. Dipal completed his MS in December 2000 with
   thesis on Method for Self-Repair of FPGAs.
2. I adapted concept of Lattices which were
   developed Dr. Perkowski and Dr. Jeske to design
   FPGA like regular structure in VLSI

This cell can be mapped to Shannon, positive
Davio, negative Davio and other logic gates.
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General idea of SRFPGA architecture

• General idea of the SRFPGA architecture, each
  circle represents cell shown on the previous
  foil.
• Row and column decoders are for memory addressing
• The next foil shows actual physical design of the
  SRFPGA

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SRFPGA layout With I/O pins
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1
Faults observed during column test C 2.
Test output
0
1 1 1 1 1 1 1 1
1 1 1 0 1 0 1 1
Var1 var2 var3 var4 var5 var6 var7 var8 v
ar9 var10 var11 var12 var13 var14 var15 var
16
1
I n p u t t e s t v e c t o r
Faults observed during diagonal test D 2
1
0
1
T e s t o u t p u t
1
1
1

1
1
1
1
1
1
Total number of Faults N C D 2 2 4.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
Input test vector
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1. Dipal developed a unique test that identifies
   any number of faulty cell in the FPGA
2. Repair is based on redundancy-repair where
   identified faulty cells are replaced with unused
   good cell in the structure
3. Later Dipal adapted concept of lattice and
   synthesis methodology for designing reversible
   logic circuits.
4. His method of reversible circuit design resolves
   many issues that are not yet addressed by any
   other researchers
5. This approach can be extended to reversible and
   quantum logic cicuits.

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• CONCLUSIONS and possible projects

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Conclusions

• Experimental results proved that our algorithm
  produced better results in terms of quantum cost
  compared to other contemporary algorithms for
  synthesis of reversible logic.
• New gate family called Dipal gate
• Presented new synthesis method with layered
  diagrams.
• More accurate technology specific cost model for
  1D qubit neighborhood architecture.

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CONCLUSIONS

• A new method based of lattice diagram to
  synthesize reversible logic circuit with 3x3
  Toffoli gates.
• A new family of gates called Dipal Gates.
• New diagrams called layered diagram that uses
  family of Dipal gate for synthesis of reversible
  logic function.
• Software for creating Lattice diagrams and
  software for creating quantum array from Lattice
  (Lattice to QA).
• Program to implement a variant of MMD algorithm.

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Possible Projects

1. Generalize to ternary logic
2. Generalize to all Dipal Gate Family gates.
3. Realization with low level pulses for NMR
   technology.
4. Development of a concept of reversible/quantum
   FPGA similar to SRFPGA
5. Extend Agrawal-Jha method for factorized
   circuits.
6. Extend the methods to many-output circuits.

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What to remember?

1. Use of PPRM in synthesis of reversible circuits.
2. The main idea of Agrawal-Jha algorithm.
3. How AJ algorithm can be improved?
4. How this algorithm can be extended to Fredkin
   gates?
5. Expansions Rules for Lattice Diagrams
6. Creating Positive Davio Lattice
7. Creating Negative Davio Lattice
8. Creating Lattice for arbitrary function with a
   mixture of Davio and Shannon Expansions.
9. Lattices for symmetric functions.
10. Transforming Positive Davio Lattice to a quantum
    array (circuit) for single output functions.

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What to remember?

1. Transforming Positive Davio Lattice to a quantum
   array (circuit) for single output functions.
2. Transforming Positive Davio Lattice to a quantum
   array (circuit) for multi-output functions.
3. Dipal gate and Dipal gate family.
4. Regular structures and their use in quantum
   computing.
5. Regularity versus LNNM model.
6. Multiple-valued Lattices for ternary logic.
7. FPGA based on 33 lattices and can they be
   adapted to quantum and reversible circuits.
8. Decomposition to pulses. Relation to quantum
   costs.