332:578 Deep Submicron VLSI Design Lecture 1 CMOS Transistor Theory

1
332578 Deep SubmicronVLSI DesignLecture 1
CMOS Transistor Theory

• David Harris and Michael Bushnell
• Harvey Mudd College and Rutgers University
• Spring 2005

Material from CMOS VLSI Design, by Weste and
Harris, Addison-Wesley, 2005
2
Outline

• Conventional non-deep submicron transistor model
• Adjustments to VT for non-ideal 2nd-order effects
• Body Effect
• Velocity Saturation
• Leakage
• Channel Length Modulation
• Mobility Variation
• Tunnelling
• Punchthrough
• Avalanche Breakdown
• Impact Ionization
• Temperature
• Summary

3
nMOS I-V Summary

• Shockley 1st order transistor models

4
Vt Dependencies

• Gate material
• Gate insulation material
• Gate insulator thickness
• Channel doping
• Impurities at Si SiO2 interface
• Vsb voltage from source to substrate
• Vt a 1/T
• -4 mV /oC High substrate doping
• -2 mV/oC Low substrate doping

5
Non Deep-Submicron Threshold Equations

• Vt Vt-mos
  Vfb
• Vt-mos 2 fb
• fb ln , bulk potential
  difference between
• Fermi level of doped intrinsic
  Si
• Cox oxide capacitance
• Qb bulk charge 2 eSi q NA 2 fb
• ni 1.45 x 1010 cm-3 at 300 oK

Ideal Vt of Ideal MOS Capacitor
Flat-band voltage point at which energy levels
go flat
Qb Cox
kT q
NA ni
(
)
6
Definitions

• po is hole concentration in semiconductor in
  equilibrium
• pp is hole concentration in semiconductor p side
  of junction
• np is e-- concentration in semiconductor in
  equilibrium
• ni is intrinsic carrier concentration in undoped
  semiconductor of both holes and e--
• k is Boltzmanns constant
• T is absolute temperature in degrees Kelvin
• NA is acceptor concentration
• ND is donor concentration
• es is dielectric constant of Si
• b q / kT (reciprocal of thermal voltage)
• E is the electric field

7
Ideal MIS Diode

• Type p semiconductor
• At V 0,
• fms energy
  difference between
  
  metal semiconductor
• c semiconductor
  electron affinity
• fms fm (c fB ) 0
• Flat-band condition usually have to apply VFB
  (flat-band voltage) to cause this to happen

Eg 2q
8
Accumulation
(Ei EF) / kT

• p0 ni e
• Energy bands when a negative voltage is applied

9
Weak Inversion

• Energy bands when small positive bias voltage is
  applied

10
Strong Inversion

• Ei at surface now below EF by 2 fB fS
• fB potential difference between EF and Ei in
  bulk
• VT voltage necessary to cause strong inversion

11
Threshold Equations

• k Boltzmanns constant 1.380 x 10-23 J/oK
• q 1.602 x 10-19 C (1 e charge)
• kT/q 0.02586 V. at 300 oK (thermal voltage)
• eSi 1.06 x 10-12 F/cm
• Intrinsic Fermi level midway between conduction
  valence bands
• p Fermi level closer to valence band
• n Fermi level closer to conduction band
• Vfb fms -
• Qfc fixed charge due to imperfections in Si
  SiO2 interface and due to doping

Qfc Cox
12
Threshold Equations

• fms fgate fSi work function difference
  between
• gate material
  Si substrate
• fms - fb - 0.9 V (NA 1 x
  1016 cm-3)
• Eg band gap energy of Si
• (1.16 0.704 x 10-3
  )5
• fms -0.2 V (NA 1 x 1016 cm-3)

Eg 2
(
)
T2 T 1108

13
Adjustments to Vt

• Change Vt by
• Changing substrate doping NA
• Changing Cox (use a different insulator) (usual
  method)
• Changing surface state charge Qfc (usual method)
• Changing T (temperature)
• Often use a layer of Silicon nitride Si3N4 eSi3N4
  7.8 on top of SiO2
• Dual dielectric process gives combined
  erelative 6
• Electrically equivalent to thinner layer of SiO2,
  higher Cox
• MOS transistors self-isolating if regions between
  devices cannot be inverted by normal circuit
  voltages

14
Example
15
OFF Transistor Behavior

• What about current in cutoff?
• Simulated results
• What differs?
• Current doesnt go
• to 0 in cutoff

16
MOS Equations

• e
• tox

• Kp process-dependent gain factor
  m Cox
• mnbulk mpbulk mnsurface
• Si 1350 450 500
  Units of cm2 / (V sec)
• Ge 3600
• GaAs 5000
• eSi 4 eo 4 x 8.854 x 10-14 F/cm
• tox 40
• For a 0.18 mm process
• Typical bn 155 W/L mA/V2
• Typical bp 77.5 W/L mA/V2

17
Geometric MOSFET View
18
Spice/Spectre Models

• LEVEL 1 Shockley equation some 2nd-order
  effects
• LEVEL 2 Based on device physics
• LEVEL 3 Semi-empirical match equations to
  real circuits based on parameters
• BSIM3 v3 3.1 Berkeley empirical deep sub-micron
  model
• Use this one all other models give incorrect
  results
• Predict too high a Vt
• Exaggerate the body effect
• Incorrectly calculate leakage currents (drain
  induced barrier lowering)
• KP major Spice/Spectre parameter
• 77 to 155 mA/V2, varies 10-20 in manufacturing
  process

19
Second-Order Effects Cannot Be Ignored
20
Ideal nMOS I-V Plot

• 180 nm TSMC process
• Ideal Models
• b 155(W/L) mA/V2
• Vt 0.4 V
• VDD 1.8 V

21
Simulated nMOS I-V Plot

• 180 nm TSMC process
• BSIM 3v3 SPICE models
• What differs?

22
Simulated nMOS I-V Plot

• 180 nm TSMC process
• BSIM 3v3 SPICE models
• What differs?
• Less ON current
• No square law
• Current increases
• in saturation

23
Velocity Saturation

• We assumed carrier velocity is proportional to
  E-field
• v mElat mVds/L
• At high fields, this ceases to be true
• Carriers scatter off atoms
• Velocity reaches vsat
• Electrons 6-10 x 106 cm/s
• Holes 4-8 x 106 cm/s
• Better model

24
Vel. Sat. I-V Effects

• Ideal transistor ON current increases with VDD2
• Velocity-saturated ON current increases with VDD
• Real transistors are partially velocity saturated
• Approximate with a-power law model
• Ids ? VDDa
• 1 lt a lt 2 determined empirically

25
Velocity Saturation

• a is velocity saturation index
• Determined empirically by curve fitting
• Long-channel or low VDD transistors a 2
• As vel. sat. increases, a approaches 1 for
  complete vel. sat.
• Saturation refers to transistor operating
  region
• Velocity Saturation refers to limiting of
  carrier velocity at high E field

26
Velocity Saturation Eqns.

• Pc and Pv are curve fitting parameters

27
a-Power Model
28
Mobility Variation

• m average carrier drift velocity (v)
• Electric Field E
• Decreases with increasing doping and with
  increasing T
• m is Spice parameter U0
• Use BSIM to model

29
Channel Length Modulation

• Reverse-biased p-n junctions form a depletion
  region
• Region between n and p with no carriers
• Width of depletion Ld region grows with reverse
  bias
• Leff L Ld
• Shorter Leff gives more current
• Ids increases with Vds
• Even in saturation

30
Chan. Length Mod. I-V

• l channel length modulation coefficient
• not feature size
• Empirically fit to I-V characteristics

31
Channel Length Modulation

• Channel length changes for short channels as Vds
  changes
• Must now be modeled
• Effective channel length Leff L Lshort
• Lshort 2 eSi (Vds (Vgs Vt))
• q NA
• Shorter length increases W/L ratio, increases b
  as Vd increases
• Gives a finite output impedance, not a pure
  current source
• More accurate model (which we must use)
• Ids KP W (Vgs Vt)2 (1 l Vds )
• 2 L
• l channel length modulation factor (Spice
  parameter LAMBDA)

32
Channel Length Modulation

• Becomes relatively more important as channels
  shorten
• l inversely dependent on channel length
• Important for analog VLSI reduces amplifier gain

33
Body Effect

• Vt gate voltage necessary to invert channel
• Increases if source voltage increases because
  source is connected to the channel
• Increase in Vt with Vsb is called the body effect
• Series devices Vsb increases as we proceed
  along series chain
• Result Channel-substrate depletion layer width
  increases
• Result Increased density of trapped carriers in
  depletion layer
• For charge neutrality to hold, channel charge
  must decrease
• Result Vsb adds to channel-substrate junction
  potential, gate-channel voltage drop increases,
  effectively get a higher Vt

34
Body Effect
35
Body Effect Model

• Vt0 Threshold voltage when Vsb 0
• Vt Vfb 2 fb 2 eSi q NA (2 fb
  Vsb)
• 
  Cox
• Vt0 g (2 fb Vsb)
  -- 2 fb
• 0.4 g 1.0
• g tox 2 q eSi NA 1
  2 q eSi NA
• eox
  Cox
• Equivalent SPICE parameters GAMMA, VT0
• NSUB is NA, PHI is fs 2 fb (surface potential
  at onset of strong inversion, i.e., Vt)
• g body effect coefficient

36
Body Effect

• Surface potential
• Is the thermal voltage

37
Leakage Sources

• Subthreshold conduction
• Transistors cant abruptly turn ON or OFF
• Junction leakage
• Reverse-biased pn junction diode current
• Gate leakage
• Tunneling through ultra thin gate dielectric
• Subthreshold leakage is the biggest source in
  modern transistors

38
Subthreshold Leakage

• Subthreshold leakage exponential with Vgs and Vds
• n is process dependent, typically 1.4-1.5
• Affects dynamic storage memory cells
• Determined empirically
• Use BSIM to model
• Increases exponential as Vt decreases or T rises

39
DIBL

• Drain-Induced Barrier Lowering
• Drain voltage also affects Vt
• High drain voltage causes subthreshold leakage to
  ________.
• h is DIBL constant
• Bowman extended a-power low model to physical
  a-power law, that included subthreshold
  conduction and velocity saturation

40
DIBL

• Drain-Induced Barrier Lowering
• Drain voltage also affects Vt
• High drain voltage causes subthreshold leakage to
  ________.
• h is DIBL constant
• Bowman extended a-power law model to physical
  a-power law, that included subthreshold
  conduction and velocity saturation

increase
41
Junction Leakage

• Reverse-biased p-n junctions have some leakage
• Is depends on doping levels
• And area and perimeter of diffusion regions
• Typically lt 0.1 fA/mm2

42
Gate Leakage

• Carriers may tunnel thorough very thin gate
  oxides
• Predicted tunneling current (from Song01)
• Negligible for older processes
• May soon be critically important
• 10 X higher for nMOS than for pMOS

43
Fowler-Nordheim Tunneling

• For very thin gate oxides,
• Current flows from gate to source or gate to
  drain by e-- tunneling through SiO2
• Exploit in High Electron Mobility Transistor
  (HEMT)
• IFN C1 W L Eox2 e
• Eox Vgs , Electric field across
  gate oxide
• tox
• E0, C1 are constants
• Limits oxide thickness as processes are scaled
  used in making EPROMS

-E0 Eox
44
Drain Punchthrough

• Drain depletion region extends to source at high
  voltages
• Lose gate control of transistor
• Used in pin I/O (pad) circuits to make Zener
  diodes
• Forces voltages to be scaled down as device sizes
  are scaled down

45
pMOSFET Punchthrough

• Avalanche breakdown for very high Vds gate has
  no control over Ids

46
Impact Ionization Hot e--

• For submicron gate lengths ltlt 1 mm, a major
  problem
• e-- get so much energy that they impact the
  drain, and dislodge holes, which are swept toward
  the grounded substrate
• Creates a substrate current
• e-- may penetrate the gate oxide and cause gate
  current
• Degrades Vt, subthreshold current, b
• Causes circuit failure
• Poor DRAM refresh times, noise in mixed
  analog-digital circuits, latchup
• Hot holes are too slow to cause trouble

47
Impact Ionization Fixes

• Solve with lightly-doped drains
• Drop VDD to 3 V. or lower
• Isubstrate Ids C1 (Vds Vdsat)C2
• C1 2.24 X 10-5 0.1 X 10-5 Vds
• C2 6.4
• Vdsat Vtm Leff Esat
• Vtm Leff Esat
• Vtm Vgs Vtn 0.13 Vbs - 0.25 Vgs
• Esat 1.10 X 107 0.25 X 107 Vgs

48
Temperature Sensitivity

• Increasing temperature
• Reduces mobility
• Reduces Vt
• ION ___________ with temperature
• IOFF ___________ with temperature
• is room temperature
• is a fitting parameter

49
Temperature Sensitivity

• Increasing temperature
• Reduces mobility
• Reduces Vt
• ION ___________ with temperature
• IOFF ___________ with temperature
• is room temperature
• is a fitting parameter

decreases
50
Temperature Sensitivity

• Increasing temperature
• Reduces mobility
• Reduces Vt
• ION ___________ with temperature
• IOFF ___________ with temperature
• is room temperature
• is a fitting parameter

decreases
increases
51
Negative Temp. Coefficient in Saturation
52
Idsat vs. Temperature
53
Benefits of Cooling

• Cooling methods
• Natural convection
• Fans and heat sinks
• Water cooling
• Thin-film refrigerators
• Liquid nitrogen cooling
• Benefits of lower T operation
• Lower threshold voltages
• Higher velocity saturation
• Higher mobility
• Power savings
• Wider depletion regions (less junction C)
• Reduced transistor wearout methods (more
  reliability)
• Problem of lower T Lower breakdown V

54
Spice Model Parameters

• Also must use process parameters in LEVEL III
  model to calculate VT0, KP, GAMMA, PHI, and
  LAMBDA
• See Section 5.3 in book

55
So What?

• So what if transistors are not ideal?
• They still behave like switches.
• But these effects matter for
• Supply voltage choice
• Logical effort
• Quiescent power consumption
• Pass transistors
• Temperature of operation

56
Modeling Consequences

• Pass transistors suffer threshold drop when
  passing the wrong value
• Do not operate well now, where Vt is significant
  fraction of VDD
• Use fully complementary transmission gates
• Use combination of low Vt and high Vt devices in
  same process to control leakage with high Vt
  devices
• Tunneling is becoming a problem
• VDD is dropping because velocity saturation and m
  degradation give less current at high VDD
• Series transistors have less velocity saturation
  than single transistors, so they are faster than
  predicted by simple model
• Particularly nMOSFETs

57
Summary

• Current Characteristics of MOSFET
• Calculation of Vt and Important 2nd-Order
  Effects
• Models in this lecture
• For pedagogical purposes only
• Obsolete for deep-submicron technology
• Real transistor parameter differences
• Much higher transistor current leakage
• Body effect less significant than predicted
• Vt is lower than predicted