Introduction to FPGA Devices

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Introduction to FPGA Devices Tools
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FPGA Devices
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World of Integrated Circuits
Integrated Circuits
Full-Custom ASICs
Semi-Custom ASICs
User Programmable
PLD
FPGA
PAL
PLA
PML
LUT (Look-Up Table)
MUX
Gates
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Two competing implementation approaches
FPGA Field Programmable Gate Array
ASIC Application Specific Integrated Circuit

• bought off the shelf
• and reconfigured by
• designers themselves

• designs must be sent
• for expensive and time
• consuming fabrication
• in semiconductor foundry

• no physical layout design
• design ends with
• a bitstream used
• to configure a device

• designed all the way
• from behavioral description
• to physical layout

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What is an FPGA?
Configurable Logic Blocks
I/O Blocks
Block RAMs
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Which Way to Go?
ASICs
FPGAs
Off-the-shelf
High performance
Low development cost
Low power
Short time to market
Low cost in high volumes
Reconfigurability
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Other FPGA Advantages

• Manufacturing cycle for ASIC is very costly,
  lengthy and engages lots of manpower
• Mistakes not detected at design time have large
  impact on development time and cost
• FPGAs are perfect for rapid prototyping of
  digital circuits
• Easy upgrades like in case of software
• Unique applications
• reconfigurable computing

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Major FPGA Vendors

• SRAM-based FPGAs
• Xilinx, Inc.
• Altera Corp.
• Atmel
• Lattice Semiconductor
• Flash antifuse FPGAs
• Actel Corp.
• Quick Logic Corp.

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Xilinx

• Primary products FPGAs and the associated CAD
  software
• Main headquarters in San Jose, CA
• Fabless Semiconductor and Software Company
• UMC (Taiwan) Xilinx acquired an equity stake in
  UMC in 1996
• Seiko Epson (Japan)
• TSMC (Taiwan)

ISE Alliance and Foundation Series Design
Software
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Xilinx FPGA Families

• Old families
• XC3000, XC4000, XC5200
• Old 0.5µm, 0.35µm and 0.25µm technology. Not
  recommended for modern designs.
• High-performance families
• Virtex (0.22µm)
• Virtex-E, Virtex-EM (0.18µm)
• Virtex-II, Virtex-II PRO (0.13µm)
• Low Cost Family
• Spartan/XL derived from XC4000
• Spartan-II derived from Virtex
• Spartan-IIE derived from Virtex-E
• Spartan-3

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Basic Spartan-II FPGA Block Diagram
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CLB Structure

• Each slice has 2 LUT-FF pairs with associated
  carry logic
• Two 3-state buffers (BUFT) associated with each
  CLB, accessible by all CLB outputs

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CLB Slice Structure

• Each slice contains two sets of the following
• Four-input LUT
• Any 4-input logic function,
• or 16-bit x 1 sync RAM
• or 16-bit shift register
• Carry Control
• Fast arithmetic logic
• Multiplier logic
• Multiplexer logic
• Storage element
• Latch or flip-flop
• Set and reset
• True or inverted inputs
• Sync. or async. control

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LUT (Look-Up Table) Functionality

• Look-Up tables are primary elements for logic
  implementation
• Each LUT can implement any function of 4 inputs

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Distributed RAM

• CLB LUT configurable as Distributed RAM
• A LUT equals 16x1 RAM
• Implements Single and Dual-Ports
• Cascade LUTs to increase RAM size
• Synchronous write
• Synchronous/Asynchronous read
• Accompanying flip-flops used for synchronous read

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Shift Register

• Each LUT can be configured as shift register
• Serial in, serial out
• Dynamically addressable delay up to 16 cycles
• For programmable pipeline
• Cascade for greater cycle delays
• Use CLB flip-flops to add depth

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Shift Register

• Register-rich FPGA
• Allows for addition of pipeline stages to
  increase throughput
• Data paths must be balanced to keep desired
  functionality

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Carry Control Logic
COUT
YB
Look-Up Table
Carry Control Logic
Y
G4 G3 G2 G1
S
D
Q
O
CK
EC
R
F5IN
BY SR
XB
Look-Up Table
Carry Control Logic
X
S
F4 F3 F2 F1
D
Q
O
CK
EC
R
CIN CLK CE
SLICE
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Fast Carry Logic

• Each CLB contains separate logic and routing for
  the fast generation of sum carry signals
• Increases efficiency and performance of adders,
  subtractors, accumulators, comparators, and
  counters
• Carry logic is independent of normal logic and
  routing resources

MSB
Carry Logic Routing
LSB
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Accessing Carry Logic

• All major synthesis tools can infer carry logic
  for arithmetic functions
• Addition (SUM lt A B)
• Subtraction (DIFF lt A - B)
• Comparators (if A lt B then)
• Counters (count lt count 1)

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Block RAM

• Most efficient memory implementation
• Dedicated blocks of memory
• Ideal for most memory requirements
• 4 to 14 memory blocks
• 4096 bits per blocks
• Use multiple blocks for larger memories
• Builds both single and true dual-port RAMs

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Spartan-II Block RAM Amounts
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Block RAM Port Aspect Ratios
1k x 4
2k x 2
4k x 1
512 x 8
256 x 16
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Basic I/O Block Structure
D
Q
Three-State
EC
FF Enable
Three-StateControl
Clock
SR
Set/Reset
D
Q
Output
EC
FF Enable
Output Path
SR
Direct Input
FF Enable
Input Path
D
Q
Registered Input
EC
SR
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IOB Functionality

• IOB provides interface between the package pins
  and CLBs
• Each IOB can work as uni- or bi-directional I/O
• Outputs can be forced into High Impedance
• Inputs and outputs can be registered
• advised for high-performance I/O
• Inputs can be delayed

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Routing Resources
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Spartan-II FPGA Family Members
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Virtex-II 1.5V Architecture
Block RAMs
Block RAMs
Block RAMs
Block RAMs
I/O Block
Configurable Logic Block
Multipliers 18 x 18
Multipliers 18 x 18
Multipliers 18 x 18
Multipliers 18 x 18
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Virtex-II 1.5V
Device CLB Array Slices Maximum I/O BlockRAM (18kb) Multiplier Blocks Distributed RAM bits
XC2V40 8x8 256 88 4 4 8,192
XC2V80 16x8 512 120 8 8 16,384
XC2V250 24x16 1,536 200 24 24 49,152
XC2V500 32x24 3,072 264 32 32 98,304
XC2V1000 40x32 5,120 432 40 40 163,840
XC2V1500 48x40 7,680 528 48 48 245,760
XC2V2000 56x48 10,752 624 56 56 344,064
XC2V3000 64x56 14,336 720 96 96 458,752
XC2V4000 80x72 23,040 912 120 120 737,280
XC2V6000 96x88 33,792 1,104 144 144 1,081,344
XC2V8000 112x104 46,592 1,108 168 168 1,490,944
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Virtex-II Block SelectRAM

• Virtex-II BRAM is 18 kbits
• Additional parity bits available in selected
  configurations

Width Depth Address Data Parity
1 16,386 130 0 N/A
2 8,192 120 10 N/A
4 4,096 110 30 N/A
9 2,048 100 70 0
18 1,024 90 150 10
36 512 80 310 30
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FPGA Nomenclature
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FPGA Tools
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Design process (1)
Design and implement a simple unit permitting to
speed up encryption with RC5-similar cipher with
fixed key set on 8031 microcontroller. Unlike in
the experiment 5, this time your unit has to be
able to perform an encryption algorithm by
itself, executing 32 rounds..
Specification (Lab Experiments)
VHDL description (Your Source Files)
Library IEEE use ieee.std_logic_1164.all use
ieee.std_logic_unsigned.all entity RC5_core is
port( clock, reset,
encr_decr in std_logic
data_input in std_logic_vector(31 downto 0)
data_output out std_logic_vector(31
downto 0) out_full in
std_logic key_input in
std_logic_vector(31 downto 0)
key_read out std_logic ) end
AES_core
Functional simulation
Synthesis
Post-synthesis simulation
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Design process (2)
Implementation
Timing simulation
Configuration
On chip testing
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Design Process control from Active-HDL
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Simulation Tools

• Many others

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Synthesis Tools

• and others

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Logic Synthesis
VHDL description
Circuit netlist
architecture MLU_DATAFLOW of MLU is signal
A1STD_LOGIC signal B1STD_LOGIC signal
Y1STD_LOGIC signal MUX_0, MUX_1, MUX_2, MUX_3
STD_LOGIC begin A1ltA when (NEG_A'0')
else not A B1ltB when (NEG_B'0') else not
B YltY1 when (NEG_Y'0') else not
Y1 MUX_0ltA1 and B1 MUX_1ltA1 or
B1 MUX_2ltA1 xor B1 MUX_3ltA1 xnor
B1 with (L1 L0) select Y1ltMUX_0 when
"00", MUX_1 when "01", MUX_2 when
"10", MUX_3 when others end MLU_DATAFLOW
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Features of synthesis tools

• Interpret RTL code
• Produce synthesized circuit netlist in a standard
  EDIF format
• Give preliminary performance estimates
• Some can display circuit schematics corresponding
  to EDIF netlist

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Implementation

• After synthesis the entire implementation process
  is performed by FPGA vendor tools

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Translation
Synthesis
Circuit netlist
Timing Constraints
Constraint Editor
Native Constraint File
Electronic Design Interchange Format
EDIF
UCF
NCF
User Constraint File
Translation
Native Generic Database file
NGD
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Sample UCF File

• Constraints generated by Synplify Pro 7.3.3,
  Build 039R
• Period Constraints
• Begin clock constraints
• End clock constraints
• Output Constraints
• Input Constraints
• Location Constraints
• End of generated constraints
• NET "clock" LOC "P88"
• NET "control(0)" LOC "P50"
• NET "control(1)" LOC "P48"
• NET "control(2)" LOC "P42"
• NET "reset" LOC "P93"
• NET "segments(0)" LOC "P67"
• NET "segments(1)" LOC "P39"
• NET "segments(2)" LOC "P62"
• NET "segments(3)" LOC "P60"

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Pin Assignment
FPGA
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Parallel Port Interface
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Constraints Editor
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Circuit netlist
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Mapping
LUT4
LUT1
FF1
LUT5
LUT2
FF2
LUT3
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Placing
FPGA
CLB SLICES
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Routing
FPGA
Programmable Connections
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Static Timing Analyzer

• Performs static analysis of the circuit
  performance
• Reports critical paths with all sources of delays
• Determines maximum clock frequency

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Static Timing Analysis

• Critical Path The Longest Path From Outputs of
  Registers to Inputs of Registers

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Static Timing Analysis

• Min. Clock Period Length of The Critical Path
• Max. Clock Frequency 1 / Min. Clock Period

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Configuration

• Once a design is implemented, you must create a
  file that the FPGA can understand
• This file is called a bit stream a BIT file
  (.bit extension)
• The BIT file can be downloaded directly to the
  FPGA, or can be converted into a PROM file which
  stores the programming information

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Resources Required Reading
Spartan FPGA devices

• Xilinx Spartan-II 2.5V FPGA Family
• Complete Data Sheet
• Module 1 Introduction Ordering Information
• Module 2 Functional Description
• http//direct.xilinx.com/bvdocs/publications/ds001
  .pdf

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Resources Required Reading
FPGA Tools
Integrated Interfaces Active-HDL with
Synplify http//www.aldec.com/Previews/active_sy
nplify.htm Integrated Synthesis and
Implementation http//www.aldec.com/Previews/synth
esis_implementation.htm
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Hands-on Session

• Enough Talking Lets Get To It!!Brace
  Yourselves!!

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ALU Schematic
arith 10
A30 B30
0
A B
1
A - B
2
A ltltlt 1
3
A gtgtgt 1
0
0
logic 10
0
A and B
1
A or B
2
A xor B
3
A xnor B
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Questions?