Introduction to Verilog HDL

1
Introduction to Verilog HDL

• Radhika S. Grover
• email rgrover_at_scudc.scu.edu
• Office hours Thursday 5 - 530 p.m.

2
Overview

• Verilog HDL is a hardware description language.
  It can be used to specify a design. It provides
  constructs to describe hardware elements. Verilog
  is similar to the C programming language in many
  ways.
• The prominent HDLs are -
  
  Verilog HDL and VHDL.
  

3
Features Benefits

• Simplicity.
• Simulation. Simulating design can uncover errors
  even without requiring hardware to be built.
• Logic synthesis. Synthesis tools can take the
  software description and generate a gate-level
  implementation.
• Verilog HDL is similar to C in many ways.

4
Modeling Techniques

• Behavioral modeling Describes the function. The
  actual hardware structure is not implied.
• Structural modeling Describes the actual
  hardware using Verilog primitives such as or,
  nand etc.
• data flow modeling has a continuous assignment
  indicated by the keyword assign.

5
Lexical constructs and data types

• Case-sensitive.
• Short Long comments // / ../
• Special Tokens -
  compiler
  directives(define etc.)
  system tasks
  functions( time etc. )
  parameter override (
  delay etc. )
• Variable names must start with alphabetic
  character or underscore followed by alphanumeric
  or underscore character.

• Constants are of type - ltwidthgtltradixgt
  ltvaluegt where
  width is optional decimal integer, radix is
  optional ( default is decimal) and can be b,o,d,h
  for binary, octal, decimal and hex .
• Physical data types are registers and different
  types of nets. Nets represent electrical
  connections I.e. wires. Nets are continuously
  driven. Registers represent storage e.g. FF,
  latch.
• Abstract data types are integer, time, real,
  event and parameter.

6
Some expressions and basic operators

• integer x,y // two integers
• reg 70 word / 8-bit wide word /
• reg 70 mem 0127 / array of 128 bytes /
• reg arr 07 / array of 8 one-bit registers /
• module module_name() / names a module /
• _at_(in1 or in2) / causes simulation to wait until
  at least one of the inputs in1 , in2 changes its
  value.

• , -, , / add, subtract, multiply, divide
• bitwise not
• bitwise or
• bitwise and
• ? conditional
• ltlt shift left
• gtgt shift right
• ! Logical not
• logical and
• logical or
• lt less than
• equal to
• lt less than or equal to

7
Half Adder ( Behavioral )
module my_adder( zero, sum, in1, in2) parameter
WIDTH 1 input WIDTH-10 in1, in2 // Note
the order in which output and reg are specified
below. This is important. output WIDTH-10
sum reg WIDTH-10 sum output zero
reg zero always _at_(in1 or in2 ) begin
sum in1 in2 if( sum 0 )
zero 1 else zero
0 end endmodule
8
Structural Model

• Used to define a netlist. A netlist is a list of
  gates with the corresponding one-bit wires (nets)
  that each gate is connected to.
• Built-in logic gates include and, or, not, nor,
  buf etc.
• An output generated by a gate in structural
  Verilog code must be declared as wire. Inputs can
  be declared as reg or wire.

9
Half Adder ( Structural )

• module half_adder( carry, sum, a, b )
  output carry, sum
  input a, b
  
  and 2 andgate(carry, a, b)
  xor 2 orgate(sum, a, b)
  endmodule

10
Control Statements

• Loop for, while, always, repeat, forever
  e.g. always 50
  sysclk sysclk/ generates
  a system clock signal with period of 100 units of
  time /
• Conditional ? , if - else, if - else - if
• multiway decoding case - endcase

11
Conditional statement

• Use if-else or if-else-if constructs
  E.g.
  if ( index gt 0 )
  begin
  
  if ( rega gt regb )
  
  result rega
  end
  
  else
  result regb
• Using ? e.g.
  muxout (sel)? in1in0

12
Loop statements

• For statement e.g.
  for ( i 0 ilt10 ii1)
  begin
  display( Memory data d is d, i, memi)
  end
• always statement e.g. always
  begin // divide by 8 clock repeat (4)
  _at_(posedge clock)
  clk8 clk8 end

13
Loop statements continued

• while statement e.g. while ( j lt 10 )
  begin 5 j j 1
  end
• forever statement forever 1000 stop

14
Case statement

• Useful for multi-way decoding. Similar to switch
  statement in C. Variants include casez -
  this includes 0,1,z matching casex -
  this includes 0,1,x,z matching

15
Functions

• make it possible to break an algorithm into
  smaller pieces allow reusability of code.
• no concept of time associated with functions.
  Execute in zero simulation time.
• must have at least one input.
• return a single value only. This value size is
  same as function size.
• Cannot call or enable tasks.
• A function is invoked when it is referenced in an
  expression.

16
Half adder - using function
Function 10 half_adder input a,
b reg c, s
begin

case ( a,b ) 2b00 begin c 0 s
0 end 2b01 begin c 0 s 1 end
2b10 begin c 0 s 1 end 2b11
begin c 1 s 0 end default begin c
1bx s 1bx end endcase half_adder
c,s end endfunction Invocation j
half_adder(1,0)
17
Task

• Similar to C procedures.
• Can contain timing control unlike functions.
• Can have zero or more arguments.
• Can have both inputs and outputs.
• Can enable other tasks and functions.
• A task invocation is a statement.

18
Task - an example

• task display
• input 310 start, end
• integer I
• begin
• for( I start I lt end I I 1 )
• display( Xd h, I,XI )
• end
• endtask
• Invocation
• display( 25, 44)

19
Blocking Procedural Assignments

• A blocking procedural must be executed before the
  execution of statements that follow it in a
  sequential block.
  
  E.g. rega 0
  rega3
  1 // a bit-select
  carry, acc rega regb // a concatenation

20
Non-blocking procedural assignment

• You can use this when you want to make several
  register assignments within the same time step
  without regard to order or dependence upon each
  other. E.g. always c 5 c
  // initially, a 0, b1, c0
  always _at_(posedge c) begin
  a lt b
  
  b lt a end
  
  At posedge c the simulator updates the
  left-hand side of each non-blocking assignment
  statement as a1, b0.

21
Synthesis

• Convert the high-level description into an
  optimized gate-level implementation.
• Synthesis tools allow us to express design
  constraints such as area, speed etc.
• The design is read, linked, mapped to the
  target ASIC library and a gate-level netlist is
  output.

22
Synthesis Process

• Design compilation parse and compile design
  into generic logic equations.
• Logic optimization minimize the number of terms
  in the logic equations.
• technology mapping the synthesized logic is
  mapped to a gate level netlist using an ASIC
  vendor library. This implementation of gate-level
  design is used to build the actual hardware.

23
Advantages of synthesis

• Reduces the time to generate a gate-level design
  from a higher-level language design.
• Debugging effort of gate design is reduced.
• Could create a more efficient design.
• Given accurate target ASIC libraries, synthesis
  guarantees to generate a design functionally
  equivalent to the source module.

24

• Why use computer aided design and programmable
  logic?
• What is FPGA? ( Field Programmable Gate Array).
• How can we use the above two to build logic
  circuits?
• Introduction to XC4010XL and XS 40 board

25

• Why use computer aided design and programmable
  logic?
• Build designs faster because the manual wiring is
  minimized
• Avoid mistakes caused by errors in wiring
• Save your designs for as long as you like in
  electronic files and recall them whenever you
  want.
• Experiment with many types of chips
• Design larger projects because tedious manual
  procedures are automated.

26

• What is FPGA? ( Field Programmable Gate Array).
• A FPGA contains logic gates and the means for
  interconnecting them within a single integrated
  circuit.
• A FPGA can be programmed using software to
  perform the functions of a logic circuit.

27

• How can we use the above two to build logic
  circuits?
• STEP 1 Get specifications
• STEP 2 Define inputs and outputs
• STEP 3 Create truth tables
• STEP 4 Derive Boolean equations
• STEP 5 Create gate-level design
• STEP 6 Simulate gate-level design
• STEP 7 Build digital circuit
• STEP 8 Debug digital circuit
  The steps highlighted can be automated.

28
More on FPGAs

• Basic building block is look-up table or LUT. A
  typical LUT has only four inputs and a small
  memory containing 16 bits.
  
• configurable logic block (CLB) In FPGAs such as
  XC4000 series three LUTs are combined with two
  flip-flops and additional circuitry to form a CLB.

29
More on FPGAs

• Programmable Switch matrices (PSM). The CLBs are
  arranged in an array with Programmable Switch
  matrices (PSMs) between the CLBs. The PSMs are
  used to route outputs from the neighbouring CLBs
  to the inputs of a CLB.
  
• How are these switches set to make the
  connections in programmable devices?

30

• How are these switches set to make the
  connections in programmable devices?
• Each switch is controlled by a storage element
  that records whether the attached switch is
  opened or closed. Changing the values in these
  storage elements changes the state of the
  switches and alters the functions of the
  programmable device.
• XC4000 devices are re-programmable.