Presentation on Design of Folded Cascode Operational Amplifier

1

• Presentation on Design of Folded Cascode
  Operational Amplifier
• By Shubhranshu Verma
• Guidance by Dr. C. R. Wie

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Elements of cascode operational amplifier

• Folded cascode CMOS Operational Amplifier consist
  of following
• Input differential amplifier with each transistor
  connected in common source mode
• Cascode transistors connected in common gate code
• Current mirror as active load for cascode
  transistors
• Constant current source for differential pair
• Biasing network for active load, differential
  amplifier and cascode transistors

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Typical circuit diagram
Figure courtesy Microelectronic Circuits by Sedra
/Smith
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Gain of the amplifier

• Gain of the single ended amplifier is
• Av GmRo
• Where Gm short circuit trans conductance
• Gmi o/vi with RL0 and
• R0 output resistance of the amplifier
• Gm 2(I/2)/Vov I/Vov gm1gm2 and
• RoR04//R06

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Gain of the amplifier

• R04 is the output resistance of the common gate
  stage whose source has the resistance of parallel
  combination of r02 and r010 where r0 is the
  internal resistance
• R04r01(gm4gmb4)r0Rs
• Where Rs is source resistance r02//r010
• R06 is the resistance looking into the current
  mirror and is given by
• R06 gm6r06r08r06r08

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Gain of the amplifier

• Overall gain of the amplifier is
• GmR0
• or
• gm1gm4r04(r02//r010)//gm6r06r08

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Slew rate of the amplifier

• When large differential input voltage is applied
  .Output cannot change instantaneously
• Therefore Q2 is cut-off and Q1 conducts the
  entire current.
• Current through Q3 IB-I
• Current through Q4 IB
• Current mirror input current at Q5 and Q7
  IB-I

Figure Courtesy Microelectronic Circuits by
Sedra/Smith
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Slew rate continued

• Due to current mirror action output current in
  the Q6 and Q8 shall also be IB-I. Therefore the
  current equal to I will flow into the capacitor
  and output will ramp up gradually.
• It is for this reason IB should be more than I by
  about 10 to 20 to avoid current mirror turning
  off.
• Slew rate I/CL

Figure Courtesy Microelectronic Circuits by
Sedra/Smith
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Slew rate continued

• Also SR 2pftVov1
• Where ft is the unity gain bandwidth
  frequency and Vov1 is the over drive voltage of
  the Q1.
• We choose I to meet the Slew rate and ft
  requirements and IB is selected higher than I
  .Total power consumption should not be exceeded
  by this selection.

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Current Distribution in AmplifierNormal
Large signal
115
115
115
115
65
115
65
15
100
0
50
100
50
100
15
100
15
65
65
All currents are in micro-ampere. Figure Courtesy
Microelectronic Circuits by Sedra /Smith
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Bad Bias ExampleNormal
Large signal
85
85
85
85
35
0
35
70
70
85
50
15
50
100
70
100
70
35
35
All currents are in micro-ampere. Figure Courtesy
Microelectronic Circuits by Sedra /Smith
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Standard current mirrors

• Standard current mirror is shown
• We calculate the minimum voltage that should be
  maintained to keep Q3 and Q1 in saturation

Figure Courtesy Microelectronic Circuits by
Sedra/Smith
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Standard current mirror continued

• Voltage at gate of Q1 (at the edge of saturation)
  VtVov
• Since the drain of Q2 and source of Q4 are at
  potential VtVov, for Q4 to remain in saturation
• VGQ4(V t V ov) (VtVov)

Figure Courtesy Microelectronic Circuits by
Sedra/Smith
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Standard current mirror continued

• Hence Q3 remain in saturation if
• VDSVGS-Vt
• Or VD-(VtVov)
• 2(VtVov)-(VtVov)-Vt
• Or VD Vt 2Vov
• Hence negative swing has to higher by Vt2Vov for
  current mirror to remain in saturation

Vt2Vov
Figure Courtesy Microelectronic Circuits by
Sedra/Smith
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Wide swing current mirror

• In this circuit voltage at the gate of Q1 and Q2
  VtVov
• Hence Q1 can remain at the edge of the saturation
  if VD1 is Vov.
• Gate voltage of Q3 for turning it ON is (Vt Vov)
  Vov

Figure Courtesy Microelectronic Circuits by
Sedra/Smith
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Wide swing current mirror

• Hence Q3 can remain on the edge of the saturation
  for VD3(Vt2Vov)-Vt 2Vov
• Hence negative swing has to higher by 2Vov above
  the ground. This circuit increases the negative
  swing by Vt. For this gate of Q2 is connected to
  drain of Q4.

2Vov
Figure Courtesy Microelectronic Circuits by
Sedra/Smith
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Comparison of current mirrors

• As it can be seen that wide swing current mirror
  increase the voltage swing range by Vt

2Vov
2VovVt
Figure Courtesy Microelectronic Circuits by
Sedra/Smith
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Design calculations

• Based on slew rate ,ft requirement and maximum
  power consumption allowed decide I and IB.
• Keep around 15 to 20 power for biasing
  networks.
• Decide Vov of each transistor based on current or
  voltage matching requirements.

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Design calculations

• Use the following equations
• gm 2Id/Vov
• r01/(?Id)
• W/L2Id/(kVov2)
• AvGmR0
• Power consumption (V dd V ss)2IB
• If the gain requirements are not met increase Id
  till specification requirements are met.

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Final schematic diagram
Wide swing current mirror
Differential amplifier
Reference current mirror
Iss
Cascode amplifier
Vbias for cascode
Vbias for current mirror
IB
Fig .courtesy Lecture notes By Dr. C. R. Wie for
EE549 class
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Current distribution
80
20
20
40
40
0
0
20
40
40
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Thank You