ECE1352F

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All Digital Phase-Locked Loop
Why design All Digital PLL?
By Selvakkumaran S
ECE1352F Topic Presentation - ADPLL
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What is an All Digital Phase-Locked Loop (ADPLL)?

• Some Analog PLLs have utilized pure digital
  components before
• e.g Charge-pump PLLs utilized Phase Frequency
  Detector consisting of 3-state finite state
  machine with two flip-flops

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What is an ADPLL? (contd.)

• All Digital PLLs consist only of digital
  components
• The first All Digital PLL was reported by Drogni
  1967

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Why All Digital PLL?
Improvements in digital designs
Progress in increasing
Progress in reducing

• Performance

• Size

• Speed

• Cost

• Reliability

Portability/ Reusability
Programmability
Testability
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Why All Digital PLL?
Solves Problems Related to Analog PLLs(APLL)

• Sensitivity to DC Drifts

• Component Saturations

• Difficulties building higher order loops

• Initial calibration and periodic adjustments

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Issues of ADPLLs versus APLLs

• Limitation on operating speed

• Chip area

• Power Consumption

• Worse jitter performance due to D/A converter
  resolution limitation

Note The above issues need further
exploration7 as some papers have reported
better ADPLL performance.
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Example ADPLL Loop Filter

• Up/Down control from the Phase Detector Controls
  the Counter value or the Digital Phase difference
  Transfer Function 1/sTi

Up/Down Counter
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Example Digital VCO (DCO)

• Up/Down Counter Value or the Phase Error is
  utilized to create the clock

N Counter
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ADPLL Design Analysis

• Z-transform technique5,6

• z domain transfer function

• Solutions within the unit circle ensures stability

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ADPLL Design Example 12
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Results 2
3.3V Supply
Process 0.35m 0.25m 0.60m 0.60m 0.50m
Approach AD Cell Based Analog (1.9V) Semi-digital AD Cell Based All-Digital
Area(mm2) 0.71 0.09 0.83 2.75 0.71
Power(mW) 100 _at_500MHz 25 105 _at_400MHz 315 _at_800MHz 39.6 _at_100MHz
Max.lock Time(cycles) lt46 lt720 lt16 lt25 lt50
Range MHz 45-510 8.5-660 300-800 360-800 50-550
Output Jitter 70ps 80ps 149ps 60ps 125ps
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Results2

• Shorter Locking in time
• Better Jitter Performance
• Better Portability (cell-based design)
• Reduced circuit complexity
• Reduced Design Time
• Note Some other papers have reported ADPLLs area
  and power statistics better than APLLs

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ADPLL Design Example 26
A Second order ADPLL
C2(Z-1)C1
2hwnS wn2
H(z)
H(S)
(Z-1)2C2(Z-1)C1
S2 2hwnS wn2
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Acquisition Behaviour6
ADPLL shows a better performance in terms of the
acquisition time
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Phase Jitter Behaviour6
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Results6

• Larger lock-in range (4.5 x APLL)
• Larger Hold-in Range than APLL
• Smaller RMS Phase Jitter
• Digital approach to design
• Software configurability/ programmability

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Summary - Why are ADPLLs better?

• Stability

• Fast Acquisition Time

• Large hold-in range

• Large lock-in range

• Better phase jitter performance

• No need for off-chip components

• Technology portability

• Testability

• Programmability

• Simpler design and faster simulation

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Future of ADPLL

• Digital IP (Intellectual Property) vendors are
  already creating ADPLL products
• As technology progress happens skew problems will
  require ADPLLs within the design components to
  synchronize the clock signal between various
  blocks

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References

1. Behzad Razavi, Design of Analog CMOS Integrated
   Circuits, McGraw-Hill, 2001
2. Ching-Che Chung and Chen-Yi Lee, An All-Digital
   Phase-Locked Loop for High Speed Clock
   Generation, IEEE J. Solid-State Circuits, vol 38,
   No.2, pp347-351, February 2003
3. Thomas Olsson and Peter Nilsson, A Digitally
   Controlled PLL Using a Standard Cell Library,
   Lund University, Sweden, www.es.lth.se/home/ton
4. Roland E. Best, Phase-Locked Loops, Design,
   Simulation and Applications, 4th Ed, McGraw-Hill,
   1999 (Chapter 4, pp177-228)
5. Venceslav F, Kroupa, Phase Lock Loops and
   Frequency Synthesis, Wiley, 2003, (Chapter 10,
   pp231-254)

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References (contd.)

• Y.R.Shayan, T.Le-Ngoc, All Digital phase-locked
  loop concepts, design and applications, IEE
  Procedings, Vol.136, Pt. F. No.1, pp53-56,
  February 1989
• Dao-Long Chen, A Power and Area Efficient CMOS
  Clock/Data Recovery Circuit for High-Speed Serial
  Interfaces, IEEE J. of Solid-state Circuits, Vol.
  31, No8, pp1170-1176, August 1996

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The End