ASIC Library Design

1
Chapter 3

• ASIC Library Design

Application-Specific Integrated CircuitsMichael
John Sebastian Smith Addison Wesley, 1997
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ASIC Library Design

• ASIC design is usually performed using a
  predefined and precharacterized library of cells
• In designing this library, the original designer
  had to optimize speed and area without knowing
  the actual application that the cells will be
  used for - i.e., how large a load they will be
  driving
• wire load
• fanout load
• Being aware of the source and effect of these
  trade-offs will make it easier to understand how
  to optimally design using the library cells

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Model of CMOS Inverter with Parasitic Resistances
and Capacitances
Figure 3.1 A model for CMOS logic delay. (a) A
CMOS inverter with load capacitance. (b) Input
and output waveforms showing the definition of
falling propagation delay tPDF. (c) The switch
model of the inverter showing parasitic
resistances and capacitances.
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Effect of Load Capacitance on Inverter Performance
Figure 3.3 Simulation of an inverter driving a
variable number of gates on its output
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Parasitic Capacitances of a CMOS Transistor
Figure 3.4 Transistor parasitic capacitance. (a)
An N-channel MOS transistor with gate length L
and width W. (b) The components of the gate
capacitance. (c) Approximating capacitances with
planar components. (d) The components of the
diffusion capacitance. (e)-(h) The dimensions of
the gate, overlap, and sidewall capacitances.
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CMOS Inverter Steady State Response
V
V
DD
DD
R
Pon
V
V
OH
DD
V
V
0
out
V
OL
out
V

f(R
,
R
)
R
M
Non
Pon
Non
RNon µ 1/WN
V
V
V
0
in
DD
in
RPon µ 1/WP
Figures from material provided with Digital
Integrated Circuits, A Design Perspective, by Jan
Rabaey, Prentice Hall, 1996
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CMOS Inverter VTC
Figures from material provided with Digital
Integrated Circuits, A Design Perspective, by Jan
Rabaey, Prentice Hall, 1996
8
The Ideal Gate
Vm Vdd/2
Figures from material provided with Digital
Integrated Circuits, A Design Perspective, by Jan
Rabaey, Prentice Hall, 1996
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Balanced CMOS Inverter
Assume that due to differences in mp and mn, for
a minimum sized transistor, Rp 2Rn For a
balanced inverter we want RP RN, so in this
case, WP must be 2WN
WP/LP 2/1
WN/LN 2/1
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Logical Effort
Figure 3.8 Logical effort. (a) The input
capacitance looking into the input capacitance of
a minimum size inverter. (b) Sizing a logic
cells transistors to have the same delay as a
minimum size inverter. (c) The logical effort of
a cell is Cin/Cinv.
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Logical Effort Of a Complex Gate
Figure 3.10 An AOI221 cell with logical effort
vector g(8/3, 8/3, 7/3).
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The Basic Trade-off
Which is faster?
to other gates (fanout)
buffer
to other gates (fanout)