A Greatest Common Divisor (GCD) Processor

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A Greatest Common Divisor(GCD) Processor

• Lecture L10.3

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Datapath of a PIC type processor
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Euclids GCD algorithm
GCD(9,15) x 9 y 15 y 15 9 6 x 9 6
3 y 6 3 3 GCD(9,15) 3
1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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GCD
clr
clk
clr
clk
Z
GCD Datapath
GCD Control Unit
C
x
r0ld
y
r1ld
wld
stld
PC
m1sel
PD
m2sel
m3sel(10)
PG
alusel(20)
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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gcdctl.abl
MODULE gcdctl interface(Clk, Clear, Z, C -gt r0ld,
r1ld, stld, wld, m1sel, m2sel, m3sel1..m3sel0,
alusel2..alusel0) TITLE 'Control Unit for GCD
algorithm' DECLARATIONS " INPUT PINS " Clk PIN
" clock Z, C PIN " zero and carry
flags Clear PIN " clear " OUTPUT PINS " r0ld,
r1ld, stld, wld PIN " reg load signals m1sel,
m2sel, m3sel1..m3sel0 PIN " mux
selects alusel2..alusel0 PIN " alu select "
INTERMEDIATE NODES Q2..Q0 PIN ISTYPE 'reg
buffer' " LED 14..16 Q Q2..Q0
" 3-bit state vector
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gcdctl.abl (cont.)
" Definitions QSTATE Q2, Q1, Q0 s0 0, 0,
0 s1 0, 0, 1 s2 0, 1, 0 s3 0, 1,
1 s4 1, 0, 0 s5 1, 0, 1 s6 1, 1,
0 s7 1, 1, 1 state_diagram QSTATE state
s0 goto s1 state s1 goto s2 state
s2 goto s3 state s3 goto s4 state s4
if Z then s7 else if C then s5 else s6
state s5 goto s2 state s6 goto s2 state
s7 goto s7
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gcdctl.abl (cont.)
EQUATIONS WHEN QSTATE s0 then " R0 lt- x
r0ld 1 r1ld 0 stld 0 wld 0
m1sel 0 m2sel 0 m3sel1..m3sel0
.X.,.X. alusel2..alusel0 0,0,0 WHEN
QSTATE s1 then " R1 lt- Y r0ld 0 r1ld
1 stld 0 wld 0 m1sel 1 m2sel 0
m3sel1..m3sel0 .X.,.X. alusel2..alusel0
0,0,0 WHEN QSTATE s2 then " W lt- R0
r0ld 0 r1ld 0 stld 0 wld 1
m1sel .X. m2sel 1 m3sel1..m3sel0
1,1 alusel2..alusel0 0,0,0 WHEN
QSTATE s3 then " W lt- R1 - W r0ld 0
r1ld 0 stld 1 wld 1 m1sel .X.
m2sel 1 m3sel1..m3sel0 1,0
alusel2..alusel0 0,1,0
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gcdctl.abl (cont.)
WHEN QSTATE s4 then " W lt- R0 r0ld 0
r1ld 0 stld 0 wld 1 m1sel .X.
m2sel 1 m3sel1..m3sel0 1,1
alusel2..alusel0 0,0,0 WHEN QSTATE
s5 then " R0 lt- W - R1 r0ld 1 r1ld 0
stld 1 wld 0 m1sel .X. m2sel 1
m3sel1..m3sel0 1,0 alusel2..alusel0
0,1,1 WHEN QSTATE s6 then " R1 lt- R1 -
W r0ld 0 r1ld 1 stld 1 wld 0
m1sel .X. m2sel 1 m3sel1..m3sel0
1,0 alusel2..alusel0 0,1,0 WHEN
QSTATE s7 then " DONE W lt- R0 r0ld 0
r1ld 0 stld 0 wld 1 m1sel .X.
m2sel 1 m3sel1..m3sel0 1,1
alusel2..alusel0 0,0,0
Q.C Clk Q.AR Clear END
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GCD
clr
clk
clr
clk
Z
GCD Datapath
GCD Control Unit
C
x
r0ld
y
r1ld
wld
stld
PC
m1sel
PD
m2sel
m3sel(10)
PG
alusel(20)
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pic4.abl
MODULE pic4 interface(clk,clr,PA3..PA0,PB3..PB0
,r0ld,r1ld,stld,wld,m3sel1..m3sel0,m2sel,m1sel,
alusel2..alusel0 -gt C,Z,PC3..PC0,PD3..PD0,P
G3..PG0) TITLE 'PIC4 microcontroller for
GCD' DECLARATIONS alu interface(A3..A0,B3..B0
, s2..s0 -gt Y3..Y0,CF,OVF,ZF,NF) alu1
FUNCTIONAL_BLOCK alu reg4bit interface(D3..D0,
clr,clk,load -gt Q3..Q0) R0 FUNCTIONAL_BLOCK
reg4bit R1 FUNCTIONAL_BLOCK reg4bit status
FUNCTIONAL_BLOCK reg4bit W FUNCTIONAL_BLOCK
reg4bit mux44 interface(A3..A0,B3..B0,C3..C
0,D3..D0,s1..s0 -gt Z3..Z0) M3
FUNCTIONAL_BLOCK mux44 mux24 interface(A3..A0,
B3..B0,S -gt Z3..Z0) M1 FUNCTIONAL_BLOCK
mux24 M2 FUNCTIONAL_BLOCK mux24
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pic4.abl (cont.)
" INPUT PINS " clk PIN " clock clr PIN "
clear PA3..PA0 PIN " 4-bit external input
PA PA3..PA0 PB3..PB0
PIN " 4-bit external input PB
PB3..PB0 r0ld, r1ld, stld, wld
PIN " register loads m1sel,m2sel PIN " mux
selects m3sel1..m3sel0 PIN m3sel
m3sel1..m3sel0 alusel2..alusel0 PIN " alu
select alusel alusel2..alusel0
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pic4.abl (cont.)
" OUTPUT PINS " C, Z PIN ISTYPE 'com' "
carry and zero flags
PG3..PG0 PIN ISTYPE 'com' " 4-bit W
output PG PG3..PG0
PC3..PC0 PIN ISTYPE 'com' " 4-bit R0
output PC PC3..PC0
PD3..PD0 PIN ISTYPE 'com' " 4-bit R1
output PD PD3..PD0
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pic4.abl (cont.)
EQUATIONS R0.load r0ld R0.clr clr R0.clk
clk R0.D3..D0 alu1.Y3..Y0 R1.load
r1ld R1.clr clr R1.clk clk R1.D3..D0
alu1.Y3..Y0 status.load stld status.clr
clr status.clk clk status.D3..D0
alu1.NF,ZF,OVF,CF W.load wld W.clr
clr W.clk clk W.D3..D0 alu1.Y3..Y0
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pic4.abl (cont.)
M3.s1..s0 m3sel M3.D3..D0
R0.Q3..Q0 M3.C3..C0 R1.Q3..Q0 M3.B3..B0
0,0,0,0 M3.A3..A0 0,0,0,0 M2.S
m2sel M2.A3..A0 M1.Z3..Z0 M2.B3..B0
M3.Z3..Z0 M1.S m1sel M1.A3..A0
PA M1.B3..B0 PB
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pic4.abl (cont.)
alu1.A3..A0 M2.Z3..Z0 alu1.B3..B0
W.Q3..Q0 alu1.s2..s0 alusel2..alusel0 C
status.Q0 Z status.Q2 PG W.Q3..Q0 PC
R0.Q3..Q0 PD R1.Q3..Q0 END pic4
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GCD
clr
clk
clr
clk
Z
GCD Datapath
GCD Control Unit
C
x
r0ld
y
r1ld
wld
stld
PC
m1sel
PD
m2sel
m3sel(10)
PG
alusel(20)
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MODULE GCD TITLE 'Greatest Common
Divisor' DECLARATIONS " Functional Blocks
" gcdctl interface(Clk, Clear, Z, C -gt r0ld,
r1ld, stld, wld, m1sel, m2sel, m3sel1..m3sel0,
alusel2..alusel0) gcd1 FUNCTIONAL_BLOCK
gcdctl pic4 interface(clk,clr,PA3..PA0,PB3..P
B0,r0ld,r1ld,stld,wld, m3sel1..m3sel0,m2sel,m1s
el,alusel2..alusel0 -gt C,Z,PC3..PC0,PD3..PD0
,PG3..PG0) pic FUNCTIONAL_BLOCK pic4 hex7seg
INTERFACE(D3..D0 -gt a,b,c,d,e,f,g) d7R
FUNCTIONAL_BLOCK hex7seg
GCD.abl
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GCD.abl (cont.)
" Inputs Pins " clock PIN 12 " 1 Hz clock
(jumper) clear PIN 70 " pushbutton
S1 x3..x0 PIN 11,7,6,5 " Left Switches S6 -
1..4 x x3..x0 "
x y3..y0 PIN 4,3,2,1 " Right Switches S7 -
1..4 y y3..y0 " y "
Output Pins " LED9..LED16 PIN 35,36,37,39,40,41,43
,44 ISTYPE 'com' a,b,c,d,e,f,g,dp PIN
15,18,23,21,19,14,17,24 ISTYPE 'com' "
Rightmost (units) 7-segment LED display
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" INTERMEDIATE NODES PG3..PG0 NODE PG
PG3..PG0 PC3..PC0 NODE PC
PC3..PC0 PD3..PD0 NODE PD
PD3..PD0 EQUATIONS gcd1.Clk
clock gcd1.Clear clear gcd1.Z pic.Z
gcd1.C pic.C
GCD.abl (cont.)
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pic.clk clock pic.clr clear pic.PA3..PA0
x pic.PB3..PB0 y pic.r0ld
gcd1.r0ld pic.r1ld gcd1.r1ld pic.stld
gcd1.stld pic.wld gcd1.wld pic.m3sel1..m3sel0
gcd1.m3sel1..m3sel0 pic.m2sel
gcd1.m2sel pic.m1sel gcd1.m1sel pic.alusel2..
alusel0 gcd1.alusel2..alusel0
GCD.abl (cont.)
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GCD.abl (cont.)
d7R.D3..D0 pic.PG3..PG0 a,b,c,d,e,f,g
d7R.a,b,c,d,e,f,g PG
pic.PG3..PG0 PC pic.PC3..PC0 PD
pic.PD3..PD0 LED9..LED12
PC LED13..LED16 PD
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test_vectors(clock,clear,x,y -gt
PC,PD,PG) .C.,1,9,15 -gt 0,0,0 .C.,0,9,15
-gt 9,0,0 .C.,0,9,15 -gt 9,15,0 .C.,0,9,15
-gt 9,15,9 .C.,0,9,15 -gt 9,15,6 .C.,0,9,1
5 -gt 9,15,9 .C.,0,9,15 -gt
9,6,9 .C.,0,9,15 -gt 9,6,9 .C.,0,9,15 -gt
9,6,13 .C.,0,9,15 -gt 9,6,9 .C.,0,9,15
-gt 3,6,9 .C.,0,9,15 -gt 3,6,3 .C.,0,9,15
-gt 3,6,3 .C.,0,9,15 -gt 3,6,3 .C.,0,9,15
-gt 3,3,3 .C.,0,9,15 -gt 3,3,3 .C.,0,9,15
-gt 3,3,0 .C.,0,9,15 -gt 3,3,3 .C.,0,9,15
-gt 3,3,3 .C.,0,9,15 -gt 3,3,3 END GCD
GCD.abl (cont.)
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GCD
clr
clk
clr
clk
Z
GCD Datapath
GCD Control Unit
C
x
r0ld
y
r1ld
wld
stld
PC
m1sel
PD
m2sel
m3sel(10)
PG
alusel(20)