Embedded System Implementation Platforms

1

• Lecture 3
• Embedded System Implementation Platforms

2
Learning Outcomes

• Identify the advantages and disadvantages of
  common embedded platforms
• Relate embedded platform advantages and system
  specifications
• Evaluate and compare alternative implementation
  platforms
• Select an appropriate implementation platform
  according to system functional and non-functional
  requirements and specifications

3
Embedded System Design Software and Hardware
(1/2)

• Embedded systems usually are delivered as a
  combination of software and hardware
• Unlike general purpose systems, where the
  hardware developer does not know which software
  the system will execute, we are here responsible
  for bothhardware and software,when developing an
  embedded system

4
Embedded System Design Software and Hardware
(1/2)

• This gives us the unique chance, and at the same
  time the daunting task to build hardware and
  software, together orchestrating a finely tuned
  solution to satisfy the customers requirements
  in functionality,
• safety, and economical feasibility.
• In other words we select a hardware
  implementation platform based on the software we
  will write and write software with the hardware
  platform in mind

5
Implementation Platform

• The hardware on which the embedded computing
  system will execute the software
• Could be a combination of platforms
• Hardware platforms
• General Purpose Processors
• RISC
• CISC
• Application-Specific Processors
• Microcontrollers
• Digital Signal Processors
• ASIPs
• Hardware Accelerators
• GPUs
• FPGAs
• Custom ICs

6
Processor technology

• The architecture of the computation engine used
  to implement a systems desired functionality
• Processor does not have to be programmable
• Processor not equal to general-purpose
  processor

Datapath
Controller
Datapath
Controller
Datapath
Controller
Control logic
index
Registers
Control logic and State register
Control logic and State register
Register file
total
Custom ALU
State register

General ALU
IR
PC
IR
PC
Data memory
Data memory
Program memory
Program memory
Data memory
Assembly code for total 0 for i 1 to
Assembly code for total 0 for i 1 to
Single-purpose (hardware)
General-purpose (software)
Application-specific
7
Processor technology

• Processors vary in their customization for the
  problem at hand

total 0 for i 1 to N loop total
Mi end loop
Desired functionality

General-purpose processor
Single-purpose processor
Application-specific processor
8
General-purpose processors

• Programmable device used in a variety of
  applications
• Also known as microprocessor
• Features
• Program memory
• General datapath with large register file and
  general ALU
• User benefits
• Low time-to-market and NRE costs
• High flexibility
• Pentium the most well-known, but there are
  hundreds of others

9
Single-purpose processors

• Digital circuit designed to execute exactly one
  program
• a.k.a. coprocessor, accelerator or peripheral
• Features
• Contains only the components needed to execute a
  single program
• No program memory
• Benefits
• Fast
• Low power
• Small size

10
Application-specific processors

• Programmable processor optimized for a particular
  class of applications having common
  characteristics
• Compromise between general-purpose and
  single-purpose processors
• Features
• Program memory
• Optimized datapath
• Special functional units
• Benefits
• Some flexibility, good performance, size and power

11
General Purpose Processors

• High Flexibility
• General Instruction Set
• Good for all applications, optimized for none
• Low development time
• Programming in high-level language
• Low/Medium Processing Power
• Medium Cost
• High Power Consumption

12
Application-Specific Processors Microcontrollers

• Medium Flexibility
• ISA optimized for control applications
• Low processing power
• Not suitable for data intensive applications
• Low power consumption
• Low cost
• Low development time

13
Application-Specific ProcessorsDSPs

• Medium Flexibility
• ISA optimized for optimized for fast execution of
  numerical algorithms necessary for analyzing
  signals
• Medium/High processing power
• Low/Medium power consumption
• Medium cost
• Low development time

14
Computer Architecture Taxonomy

• Unified vs separate memories
• Von Neumann vs Harvard
• Instruction format
• RISC vs CISC vs VLIW
• Data
• Register-Memory vs Load-Store vs Accumulator

15
Accumulator

• One operand implicitly in accumulator, the other
  in memory and result in accumulator

16
Register - Memory
One operand is in a register the other in memory
and the result is stored in a register
17
Register Register/ Load Store
Both operands and result are stored in registers
18
Instruction Format

• Variable length (x86)
• Fixed length (ARM, MIPS, PowerPC)
• Hybrid (MIPS16, Thumb, TI TMS320C54x)

19
The 8051 microcontroller

• a Harvard architecture (separate instruction/data
  memories)
• single chip microcontroller (µC)
• developed by Intel in 1980 for use in embedded
  systems.
• today largely superseded by a vast range of
  faster and/or functionally enhanced
  8051-compatible devices manufactured by more than
  20 independent manufacturers

20
Block Diagram
External interrupts
On-chip ROM for program code
Timer/Counter
Interrupt Control
Timer 1
On-chip RAM
Counter Inputs
Timer 0
CPU
Serial Port
Bus Control
4 I/O Ports
OSC
TxD RxD
P0 P1 P2 P3
Address/Data
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Registers
22
The MOV Instruction Addressing Modes

• MOV dest,source dest source
• MOV A,72H A72H
• MOV A, r Ar OR 72H
• MOV R4,62H R462H
• MOV B,0F9H Bthe content of F9th byte of RAM
• MOV DPTR,7634H
• MOV DPL,34H
• MOV DPH,76H
• MOV P1,A mov A to port 1
• Note 1
• MOV A,72H ? MOV A,72H
• After instruction MOV A,72H the content of
  72th byte of RAM will replace in Accumulator.
• 8086 8051
• MOV AL,72H MOV A,72H

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• Arithmetic Instructions
• ADD A, Source AASOURCE
• ADD A,6 AA6
• ADD A,R6 AAR6
• ADD A,6 AA6 or AAR6
• ADD A,0F3H AA0F3H

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• Set and Clear Instructions
• SETB bit bit1
• CLR bit bit0
• SETB C CY1
• SETB P0.0 bit 0 from port 0 1
• SETB P3.7 bit 7 from port 3 1
• SETB ACC.2 bit 2 from ACCUMULATOR 1
• SETB 05 set high D5 of RAM loc. 20h
• Note
• CLR instruction is as same as SETB
• i.e
• CLR C CY0
• But following instruction is only for CLR
• CLR A A0

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• SUBB A,source AA-source-CY
• SETB C CY1
• SUBB A,R5 AA-R5-1
• ADC A,source AAsourceCY
• SETB C CY1
• ADC A,R5 AAR51

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• DEC byte bytebyte-1
• INC byte bytebyte1
• INC R7
• DEC A
• DEC 40H 4040-1
• CPL A 1s complement
• Example
• MOV A,55H A01010101 B
• L01 CPL A
• MOV P1,A
• ACALL DELAY
• SJMP L01
• NOP RET RETI
• All are like 8086 instructions.

? CALL
27

• Logic Instructions
• ANL byte/bit
• ORL byte/bit
• XRL byte
• EXAMPLE
• MOV R5,89H
• ANL R5,08H

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Rotate Instructions
                                 

• RR A Accumulator rotate right
•   
• RL A Accumulator Rotate left 
• RRC A Accumulator Rotate right through the
  carry. 
• RLC A Accumulator Rotate left through the carry. 
  

                                 
                                    
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Structure of Assembly language and Running an
8051 program

• ORG 0H
• MOV R5,25H
• MOV R7,34H
• MOV A,0
• ADD A,R5
• ADD A,12H
• HERE SJMP HERE
• END

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Addressing Modes

• Immediate
• Register
• Direct
• Register Indirect
• Indexed

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Immediate Addressing Mode

• MOV A,65H
• MOV A,A
• MOV R6,65H
• MOV DPTR,2343H
• MOV P1,65H
• Example
• Num EQU 30
• MOV R0,Num
• MOV DPTR,data1
• ORG 100H
• data1 db Example

32
Direct Addressing Mode

• Although the entire of 128 bytes of RAM can be
  accessed using direct addressing mode, it is most
  often used to access RAM loc. 30 7FH.
• MOV R0, 40H
• MOV 56H, A
• MOV A, 4 MOV A, R4
• MOV 6, 2 copy R2 to R6
• MOV R6,R2 is invalid !
• SFR register and their address
• MOV 0E0H, 66H MOV A,66H
• MOV 0F0H, R2 MOV B, R2
• MOV 80H,A MOV P1,A

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Register Indirect Addressing Mode

• In this mode, register is used as a pointer to
  the data.
• MOV A,_at_Ri move content of RAM loc.Where
  address is held by Ri into A
• ( i0 or 1 )
• MOV _at_R1,B
• In other word, the content of register R0 or R1
  is sources or target in MOV, ADD and SUBB
  insructions.
• Example
• Write a program to copy a block of 10 bytes from
  RAM location sterting at 37h to RAM location
  starting at 59h.
• Solution
• MOV R0,37h source pointer
• MOV R1,59h dest pointer
• MOV R2,10 counter
• L1 MOV A,_at_R0
• MOV _at_R1,A
• INC R0
• INC R1
• DJNZ R2,L1

• jump

34
Indexed Addressing Mode And On-Chip ROM Access

• This mode is widely used in accessing data
  elements of look-up table entries located in the
  program (code) space ROM at the 8051
• MOVC A,_at_ADPTR
• A content of address A DPTR from ROM
• Note
• Because the data elements are stored in the
  program (code ) space ROM of the 8051, it uses
  the instruction MOVC instead of MOV. The C
  means code.

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MUL DIV

• MUL AB BA AB
• MOV A,25H
• MOV B,65H
• MUL AB 25H65H0E99
• B0EH, A99H
• DIV AB A A/B, B A mod B
• MOV A,25
• MOV B,10
• DIV AB A2, B5

36
Stack in the 8051

• The register used to access the stack is called
  SP (stack pointer) register.
• The stack pointer in the 8051 is only 8 bits
  wide, which means that it can take value 00 to
  FFH. When 8051 powered up, the SP register
  contains value 07.

37
Example MOV R6,25H MOV R1,12H MOV R4,0F3H
PUSH 6 PUSH 1 PUSH 4
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Example (cont.)

• POP 4
• POP 1
• POP 6

39
LOOP and JUMP Instructions

• DJNZ
• Write a program to clear ACC, then
• add 3 to the accumulator ten times
• Solution
• MOV A,0
• MOV R2,10
• AGAIN ADD A,03
• DJNZ R2,AGAING repeat until R20 (10 times)
• MOV R5,A

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• Other conditional jumps

JZ Jump if A0
JNZ Jump if A/0
DJNZ Decrement and jump if A/0
CJNE A,byte Jump if A/byte
CJNE reg,data Jump if byte/data
JC Jump if CY1
JNC Jump if CY0
JB Jump if bit1
JNB Jump if bit0
JBC Jump if bit1 and clear bit
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• SJMP and LJMP
• LJMP(long jump)
• LJMP is an unconditional jump. It is a 3-byte
  instruction in which the first byte is the
  opcode, and the second and third bytes represent
  the 16-bit address of the target location. The
  20byte target address allows a jump to any memory
  location from 0000 to FFFFH.
• SJMP(short jump)
• In this 2-byte instruction. The first byte is
  the opcode and the second byte is the relative
  address of the target location. The relative
  address range of 00-FFH is divided into forward
  and backward jumps, that is , within -128 to 127
  bytes of memory relative to the address of the
  current PC.

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CJNE , JNC

• Exercise
• Write a program that compare R0,R1.
• If R0gtR1 then send 1 to port 2,
• else if R0ltR1 then send 0FFh to port 2,
• else send 0 to port 2.

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(No Transcript)
44
INTRODUCTION

• ARM is a RISC processor.
• It is used for small size and high performance
  applications.
• Simple architecture low power consumption.

45
TIMELINE (1/2)

• 1985 Acorn Computer Group manufactures the first
  commercial RISC microprocessor.
• 1990 Acorn and Apple participation leads to the
  founding of Advanced RISC Machines (A.R.M.).
• 1991 ARM6, First embeddable RISC microprocessor.
  
• 1992 1994 Various companies use ARM (Sharp,
  Shamsung), while in 1993 ARM7, the first
  multimedia microprocessor is introduced.

46
TIMELINE (2/2)

• 1995 Introduction of Thumb and ARM8.
• 1996 2000 Alcatel, Huindai, Philips, Sony, use
  ?RM, while in 1999 ? ARM cooperates with Erickson
  for the development of Bluetooth.
• 2000 2002 ARMs share of the 32 bit embedded
  RISC microprocessor market is 80. ARM Developer
  Suite is introduced.

47

• THE ARM ARCHITECTURE

48
GENERAL INFO (1/2)

• AIM Simple design
• Load store architecture
• 32 bit data bus
• 3 addressing modes

49
Ge???? (2/2)

• Simple architecture
• Simple instruction set
• Code density

• Small size
• Low power consumption

50
Registers

• 32 general purpose registers
• 7 modes of operation
• Different set of visible registers and different
  cpsr control level in each mode.

51
?? ??at?? ?ata????t?? t?? ARM
r0
usable in user mode
r1
r2
system modes only
r3
r4
r5
r6
r7
r8_fiq
r8
r9_fiq
r9
r10_fiq
r10
r1
1_fiq
r1
1
r13_und
r13_irq
r12_fiq
r13_abt
r12
r14_und
r13_svc
r14_irq
r13_fiq
r14_abt
r13
r14_svc
r14_fiq
r14
r15 (PC)
SPSR_und
SPSR_irq
SPSR_abt
SPSR_svc
CPSR
SPSR_fiq
svc
abort
irq
undefi
ned
fiq
user mode
mode
mode
mode
mode
mode
52
CPSR

• N Negative
• Z Zero
• C Carry
• V Overflow
• Q Saturation (for enhanced DSP instructions)

ARM CPSR format
53
Memory Organization

• Address bus 32 bits
• 1 word 32 bits

54
Instruction Set

• Three instruction types
• Data processing
• Data transfer
• Control flow

55
Supervisor mode

• In user mode the operating system handles
  operations outside user privileges.
• Using supervisor calls, the user goes to system
  level and can perform system functions.

56
I/O System

• ARM handles peripherals as memory mapped devices
  with interrupt support.
• Interrupts
• IRQ normal interrupt
• FIQ fast interrupt

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Exceptions

• Exceptions
• Interrupts
• Supervisor Call
• Traps
• When an exception takes place
• The value of PC is copied to r14_exc
• The operating mode changes into the respective
  exception mode.
• The PC takes the exception handler vector
  address.

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ARM programming model
r0
usable in user mode
r1
r2
system modes only
r3
r4
r5
r6
r7
r8_fiq
r8
r9_fiq
r9
r10_fiq
r10
r1
1_fiq
r1
1
r13_und
r13_irq
r12_fiq
r13_abt
r12
r14_und
r13_svc
r14_irq
r13_fiq
r14_abt
r13
r14_svc
r14_fiq
r14
r15 (PC)
SPSR_und
SPSR_irq
SPSR_abt
SPSR_svc
CPSR
SPSR_fiq
svc
abort
irq
undefi
ned
fiq
user mode
mode
mode
mode
mode
mode
59

• THE ARM
• INSTRUCTION SET

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Data Processing Instructions (1/2)

• Arithmetic Operations
• ADD r0, r1, r2 r0 r1r2 and dont update
  flags
• ADDS r0, r1, r2 r0 r1r2 and update
  flags
• Logical Operations
• AND r0, r1, r2 r0 r1 AND r2
• Register Movement
• MOV r0, r2
• Comparison
• CMP r1, r2

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Data Processing Instructions (2/2)

• Operands
• Immediate operands
• ADD r3, r3, 1
• Shifted register operands
• ADD r3, r2, r1, LSL 3
• Miscellaneous data processing instructions
• Multiplication
• MUL r4, r3, r2

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Data transfer instructions

• Load and store instructions
• LDR r0, r1
• STR r0, r1
• Offset LDR r0, r1,4
• Post indexed LDR r0, r1, 16
• Auto indexed LDR r0, r1,16!
• Multiple data transfers
• LDMIA r1, r0,r2,r5

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Examples

• PRE
• r0 0x00000000
• r1 0x00009000
• mem320x00009000 0x01010101
• mem320x00009004 0x02020202
• LDR r0, r1, 4!
• POST
• r0 0x02020202
• r1 0x00009004

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Examples

• PRE
• r0 0x00000000
• r1 0x00009000
• mem320x00009000 0x01010101
• mem320x00009004 0x02020202
• LDR r0, r1, 4
• POST
• r0 0x02020202
• r1 0x00009000

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Examples

• PRE
• r0 0x00000000
• r1 0x00009000
• mem320x00009000 0x01010101
• mem320x00009004 0x02020202
• LDR r0, r1, 4
• POST
• r0 0x01010101
• r1 0x00009004

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Examples

• mem320x80018 0x03
• mem320x80014 0x02
• mem320x80010 0x01
• r0 0x00080010
• LDMIA r0!, r1-r3
• r0 0x0008001c
• r1 0x00000001
• r2 0x00000002
• r3 0x00000003

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Examples

• mem320x8001c 0x04
• mem320x80018 0x03
• mem320x80014 0x02
• mem320x80010 0x01
• r0 0x00080010
• LDMIB r0!, r1-r3
• r0 0x0008001c
• r1 0x00000002
• r2 0x00000003
• r3 0x00000004

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Conditional execution
69
Control flow instructions

• Branch instruction B label
• Conditional branch BNE label
• Branch and Link BL label
• BL loop
• Loop
• MOV PC, r14 return

70
Common DSP features

• Harvard architecture
• Dedicated single-cycle Multiply-Accumulate (MAC)
  instruction (hardware MAC units)
• Single-Instruction Multiple Data (SIMD) Very
  Large Instruction Word (VLIW) architecture
• Pipelining
• Saturation arithmetic
• Zero overhead looping
• Hardware circular addressing
• Cache
• DMA

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Harvard Architecture

• Physically separate memories and paths for
  instruction and data

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Single-Cycle MAC unit
Can compute a sum of n-products in n cycles
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Single Instruction - Multiple Data (SIMD)

• A technique for data-level parallelism by
  employing a number of processing elements working
  in parallel

74
Very Long Instruction Word (VLIW)

• A technique for instruction-level parallelism by
  executing instructions without dependencies
  (known at compile-time) in parallel
• Example of a single VLIW instruction
• Fab ce/g dxy wzh

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CISC vs. RISC vs. VLIW
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Pipelining

• DSPs commonly feature deep pipelines
• TMS320C6x processors have 3 pipeline stages with
  a number of phases (cycles)
• Fetch
• Program Address Generate (PG)
• Program Address Send (PS)
• Program ready wait (PW)
• Program receive (PR)
• Decode
• Dispatch (DP)
• Decode (DC)
• Execute
• 6 to 10 phases

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Saturation Arithmetic

• fixed range for operations like addition and
  multiplication
• normal overflow and underflow produce the maximum
  and minimum allowed value, respectively
• Associativity and distributivity no longer apply
• 1 signed byte saturation arithmetic examples
• 64 69 127
• -127 5 -128
• (64 70) 25 122 ? 64 (70 -25) 109

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Lecture 5

• The TMS320C6x Family of DSPs

79
Features

• High-Performance Fixed-Point Digital Signal
  Processor (TMS320C6413/C6410)
• - TMS320C6413
• 2-ns Instruction Cycle Time
• 500-MHz Clock Rate
• 4000 MIPS
• - TMS320C6410
• 2.5-ns Instruction Cycle Time
• 400-MHz Clock Rate
• 3200 MIPS
• Eight 32-Bit Instructions/Cycle

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Features

• Eight Highly Independent Functional Units
• Six ALUs (32-/40-Bit), Each Supports Single
  32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per
  Clock Cycle
• Two Multipliers Support Four 16 x 16-Bit
  Multiplies (32-Bit Results) per Clock Cycle or
  Eight 8 x 8-Bit Multiplies (16-Bit Results) per
  Clock Cycle
• Load-Store Architecture
• 64 32-Bit General-Purpose Registers
• Instruction Packing Reduces Code Size
• All Instructions Conditional

81
Features

• L1/L2 Memory Architecture
• - 128K-Bit (16K-Byte) L1P Program Cache (Direct
  Mapped)
• - 128K-Bit (16K-Byte) L1D Data Cache (2-Way
  Set-Associative)
• - 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache
  C6413
• - 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache
  C6410
• Endianess Little Endian, Big Endian
• - 512M-Byte Total Addressable External Memory
  Space
• Enhanced Direct-Memory-Access (EDMA) Controller
  (64 Independent Channels)
• 16 prioritized interrupts

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Block Diagram
83
Programming the TMS320C6x Family of DSPs

• Programming model
• Assembly language
• Assembly code structure
• Assembly instructions
• C/C
• Intrinsic functions
• Optimizations
• Software Pipelining
• Inline Assembly
• Calling Assembly functions
• Using Interrupts
• Using DMA

84
Programming model

• Two register files A and B
• 16 registers in each register file (A0-A15),
  (B0-B15)
• A0, A1, B0, B1 used in conditions
• A4-A7, B4-B7 used for circular addressing

85
Assembly language structure

• A TMS320C6x assembly instruction includes up to
  seven items
• Label
• Parallel bars
• Conditions
• Instruction
• Functional unit
• Operands
• Comment
• Format of assembly instruction
• Label parallel bars condition instruction unit
  operands comment

86
Parallel bars

• indicates that current instruction executes
  in parallel with previous instruction, otherwise
  left blank

87
Condition

• All assembly instructions are conditional
• If no condition is specified, the instruction
  executes always
• If a condition is specified, the instruction
  executes only if the condition is valid
• Registers used in conditions are A1, A2, B0, B1,
  and B2
• Examples
• A executes if A ? 0
• !A executes if A 0
• B0 ADD .L1 A1,A2,A3
• !B0 ADD .L2 B1,B2,B3

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Instruction

• Either directive or mnemonic
• Directives must begin with a period (.)
• Mnemonics should be in column 2 or higher
• Examples
• .sect data creates a code section
• .word value one word of data

89
Functional units (optional)

• L units 32/40 bit arithmetic/compare and 32 bit
  logic operations
• S units 32-bit arithmetic operations, 32/40-bit
  shifts and 32-bit bit-field operations, 32-bit
  logical operations, Branches, Constant
  generation, Register transfers to/from control
  register file (.S2 only)
• M units 16 x 16 multiply operations
• D units 32-bit add, subtract, linear and
  circular address calculation, Loads and stores
  with 5-bit constant offset, Loads and stores with
  15-bit constant, offset (.D2 only)

90
Operands

• All instructions require a destination operand.
• Most instructions require one or two source
  operands.
• The destination operand must be in the same
  register file as one source operand.
• One source operand from each register file per
  execute packet can come from the register file
  opposite that of the other source operand.
• Example
• ADD .L1 A0,A1,A3
• ADD .L1 A0,B1,A2

91
Instruction format

• Fetch packet
• The same functional unit cannot be used in the
  same fetch packet
• ADD .S1 A0, A1, A2 .S1 is used for
• SHR .S1 A3, 15, A4 ...both instructions

92
Arithmetic instructions

• Add/subtract/multiply
• ADD .L1 A3,A2,A1 A1?A2A3
• SUB .S1 A1,1,A1 decrement A1
• MPY .M2 A7,B7,B6 multiply LSBs
• MPYH .M1 A7,B7,A6 multiply MSBs

93
Move and Load/store Instructions- Addressing Modes

• Loading constants
• MVK .S1 val1, A4 move low halfword
• MVKH .S1 val1, A4 move high halfword
• Indirect Addressing Mode
• LDH .D2 B2, B7 load halfword B7?B2,
  increment B2
• LDH .D1 A2, A7 load halfword A7?A2,
  increment A2
• STW .D2 A1, A420 store A420 words ? A2,
  preincrement/dont modify A4

94
Example

• Calculate the values of register and memory for
  the following instructions
• A2 0x00000010, MEM0x00000010 0x0,
  MEM0x00000014 0x1, MEM0x00000018 0x2,
  MEM0x0000001C 0x3,
• LDH .D1 A2, A7 A2 ? A7 ?
• LDH .D1 A2--2, A7 A2 ? A7 ?
• LDH .D1 -A2, A7 A2 ? A7 ?
• LDH .D1 A22, A7 A2 ? A7 ?

95
Branch and Loop Instructions

• Loop example
• MVK .S1 count, A1 loop counter
• MVKH .S2 count, A1
• LOOP MVK .S1 val1, A4 loop MVKH .S1 val1,
  A4 body
• SUB .S1 A1,1,A1 decrement counter
• A1 B .S2 Loop branch if A1 ? 0
• NOP 5 5 NOPs for branch

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Programmable Logic Devices

• All layers (diffusion, polysilicon, multi-
  metal) may exist
• Designers can purchase an IC
• Connections on the IC are either created or
  destroyed to implement desired functionality
• Field-Programmable Gate Array (FPGA) and recently
  Gate Arrays are very popular
• Benefits
• Low NRE costs, almost instant IC availability
• Drawbacks
• Bigger, expensive (perhaps 30 per unit), power
  hungry, slower

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Xilinx XC4000 FPGA

• CLBs are configured to implement simple logic

98
XC4000 CLB
99
Xilinx Zynq-7000 Extensible Processing Platform
(EPP) Dual Cortex A9 FPGA SoC

• dual-core ARM Cortex-A9
• 28-nm programmable digital FPGA
• programmable analog capabilities
• automotive (video processing and analytics
  requirements for driver assistance systems),
• broadcast (high-bit-rate bandwidth for
  high-accuracy video processing and analytics),
• industrial control

100
Platform-Based Design
Only the consumer gets freedom of
choice designers need freedom from
choice (Orfali, et al, 1996, p.522)

• A platform is a restriction on the space of
  possible implementation choices, providing a
  well-defined abstraction of the underlying
  technology for the application developer
• New platforms will be defined at the
  architecture-micro-architecture boundary
• They will be component-based, and will provide a
  range of choices from structured-custom to fully
  programmable implementations
• Key to such approaches is the representation of
  communication in the platform model

SourceR.Newton
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Platform-based Design System-on-Chip

• Use of predefined Intellectual Property (IP)
• A platform-based system consists of a RISC
  processor, memories, busses and a common language
• Platform-based design poses the problem of
  partitioning a solution between hardware (HDL)
  and software (programming processors)

102
Platforms Enable Simplified SoC Design

• Customer demands
• Fast turn-around time
• Easy access to pre-qualified building blocks
• Web enabled
• Design technology
• Core platforms
• Big IP
• Emerging SoC bus standards
• Embedded software
• HW/SW co-verification

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And Automation of IP Selection Integration
104
Heterogeneous Programmable Platforms
FPGA Fabric
Embedded memories
Embedded PowerPc
Hardwired multipliers
Xilinx Vertex-II Pro
High-speed I/O
105
Xilinxs products
106
Xilinxs products
107
Comparison of CMOS design methods/ Implementation
Platforms
Design Method NRE Unit Cost Power Dissipation Complexity of Implementation Time-to-Market Performance Flexibility
µProcessor/DSP low medium high low low low high
PLA low medium medium low low medium low
FPGA low high medium medium medium medium medium
Gate/Array medium medium low medium medium medium medium
Cell Based high low low high high high low
Custom Design high low low high high Very high low
Platform Based high Low/medium low high Medium/low high medium