University of Liverpool

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Beetle Hybrid testresults

• ????? ?????????
• University of Liverpool

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Introduction

• First LHCb VeLo module assembly and test
• completed design of VeLo hybrid
• assembling with Beetle chips
• comparison of Beetle 1.2 and 1.3 on the same
  hybrid
• data acquisition setup
• noise - calibration measurements

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Hybrid June 2003

• Produced in CERN for evaluation purpose and debug
• bonded with carbon fiber
• populated initially with 8 Beetle 1.2 and then
  in September with other 8 Beetle 1.3
• Status all chips are working quite stable for
  long time.

Designed by T. Smith
Thanks P. Cooke
Thanks M. Wormald
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Hybrid once more
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Pitch adapters September 2003

• Nedded to be opened for bonding and treated in
  the ionizing owen

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MotherBoard

• Produced by Lausanne, Raymond Frey
• used 8 interchangeble mezzanine cards, 8
  differential channels each

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MotherBoard

• Some problems are at the beginning due to the low
  bandwidth and terminations of the lines - seams
  now resoved.

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DAQ March 2003

CERN system We copied Jan Buyetaerts system
developed for NA60

• 8 channel ADC
• including timing signals and TDC
• s-link communication for data transfer
• i2c on parallel port

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DAQ January 2003

VME system

• Single board computer
• 8 channel Jorger ADC
• SeqSi sequencer
• i2c on parallel port
• it is awaiting also MUX for the system to fit 16
  chips output (4 cahnnels each) to the
  8 cannels input ADCs and to facilitate automatic
  test proceedure.

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DAQ compare
VME system
CERN system

• available routines for online analysis and
  monitoring
• flexible to build any application in LV or for
  offline (routines available)
• need some hardware to use with source
  measurements

• fast data transfer
• self consisted - has timing and TDC inside
• format is compatible test beam
• offline can use software from test beam
• s-link works unreliably
• management is not very flexible
• need to proceed to offline

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DAQ - software

• LabView programs were developed to monitor online
  all 8 channels on VME system. The online
  calculation pedestal-noise is applied.
• Small routines to load timing sequence for
  different test purposes
• I2C communication with chips by LabView
• in CERN system possibility to use implemented TDC
  and test beam software for offline analysis

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Power consumption

• For the fully assembled 16 chips hybrid
• Switching on of the hybrid 0.8 A
• each chip loaded - 200 ua
• totally loaded hybrid 4 A
• gt 0.25 A/chip - 0.625 W

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Bandwidth problems
There is quite some problems with bandwidth,
influence first channel and even channel after
one with TP applied. - the use of new apmlifier
on the motherboard resolves this problem.
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Pedestals
The Beetle chip can work in two modes - 1 port
mode - 128 channels in one output and fast 4
port mode - parallel reading of groups of 32
channels There is quite some difference in
pedestals if it is used 1 or 4 port output mode
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Noise
Noise as well is 1 or 4 port output mode
dependant. CM calculated for 128 strips
Noise 1.2 10-12 ADC (1 port) 10-12 ADC (4
ports) 1.3 27-42 ADC 3.5-4.5 ADC
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Internal calibration

• there is routine written to perform test of
  internal calibration
• Gain spread 10
• 28-32 ADC/ Itp unit

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????????? ???? - Plans

• Improve the post amplification stage
• Bond with R sensor - in order to perform noise
  calibration with a source.
• Test with cooling at operating temperature.
• Test in vacuum environment.
• To improve the design of the pitch adapters and
  assembly
• ???
• Install in LHCb area

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Conclusions

• The module is up to be completed within January
  2004
• In Liverool laboratory we are able to test it
  with source and
• laser in order to calibrate and to descover
• improvement/weak points of the new generation
  electronics
• (Beetle) and be able to demand on new generation
  of chip
• (still in time ?).

Thanks to whole Liverpool group