3%20%20Process%20and%20Device%20Physics

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3 Process and Device Physics

• 1. Quantum-Theoretical Definition of
  Semiconductor
• 2. PN Diode
• 3. MOS(Metal-Oxide-Semiconductor) Capacitor
  Theory
• 4. Ideal MOSFET I-V Relations
• 5. Actual MOSFET(Secondary Effects)
• 6. CMOS Process
• 7. CMOS Layout Design Rules
• 8. SPICE Model for MOSFET

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1. Quantum Theoretical Definition of Semiconductor

• Semiconductor No.1 Property
• Two charge carriers(electron hole)
  existing in energy bands separated by Eg
• Two important facts about semiconductor(or
  Semiconducting Crystal) Band Gap Fermi Level
• Band Gap(between Conduction Valence band)
• Discrete energy levels in Isolated Quantum Well

Energy level
E0
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• Perturbation of discrete energy levels in
  multiple QWs in interacting distance(plus the
  effect of finiteness of energy wall)
• Energy level becomes Energy band

Eg (Energy Gap)
EF(Fermi Level)
nucleus

• If the structure is non-periodic, the allowed
  energy levels constitute continuum.

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Fermi Level(P(EF)0.5 always)

• According to Fermi-Dirac Statistics, P(E)
  Probability of energy level, E being occupied by
  a particle, is

1

1exp(E-EF)/kT
free electron
empty
T?0
T0
Ec
E
EF
EF
Eg
Ev
hole
0.5
P(E)
E0
full
P(E)
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Fermi Level(cont)

• Impurity-doped Semiconductor electron hole
  populations are unbalanced by doping n-type
  p-type atoms, respectively.

(p-type Semiconductor)
Ec
EF
EF
Ev
(n-type Semiconductor)
Deficit of electron hole
Excess electron
Silicon
Phosphorus
Silicon
Boron
(p-type Semiconductor)
(n-type Semiconductor)
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2. P-N Diode
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• In Equilibrium, particle movement, in macroscopic
  sense, has stopped(i.e., no current flow in case
  of charged particle) therefore Fermi level is
  constant throughout all locations in equilibrium,
  i.e., connected and unbiased

(p-type Semiconductor)
(n-type Semiconductor)
EFN
EFP
Ec
EF
EV
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Forward bias
VF
Reverse bias
I
VB
VR
V
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3. MOS Capacitor Theory

• MOS Capacitor combination of Metal, (Perfect
  Conductor), Oxide(Perfect Insulator in DC Sense,
  and good Dielectric in AC sense), and
  Semiconductor substrate.

(Oxide)
(M)
(O)
(S)
? S,P
? M
? S,P
? M
Ec
EFM
EFS,P
(metal)
EV
V0
(p-type silicon)
separation
Deple -tion Region
Minimal energy an electron needs to escape
from inside metal(silicon) to air
P-Si
?M(? S)
V
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• Flat-band voltage(VFB)

Qfc
VFB ?MS -
flat-band condition
Cox
?MS ?M - ?S(Work Function Difference) Qfc
Fixed charge per area Cox Oxide capacitance per
unit area
VVFB
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• Threshold voltage (VT)

Inversion condition
QB Cox
Xd
VT VFB 2?F
Ec
Ei - EF q
?s
?F
Ei
?F
EF
QB charge per unit surface area qNAXD
(M)
(O)
(P-Si)
X0
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From Gauss Theorem, ??D ??E - ?(x)
As ,
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VBS Bulk(Substrate) to Source (reverse) bias
voltage
body effect constant
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• Surface Conditions Accumulation - Flat-Band -
  Inversion

VltVFB
VgtVT
VVFB
4)
1) VVFB
3)
xd
2) V0
Xd,max
2)
3) VVT
1)
4) VgtVT
1, 2 immobile charge(ionized impurity) 3, 4
mobile charge(electron)
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Capacitance-Voltage Plot (C/V Plot)
vo _at_ -jwRCvi
voµC
Low frequency, or MOSFET structure
(w ltltgeneration rate)
High frequency pulsed V(deep depletion)
n
p
n diffusion prompt supplier of electron
Thermal generation of e,h-pair
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4. Ideal MOSFET I/V Relations
n-ch MOSFET
n
n
p-sub
p-ch MOSFET
p
p
n-sub
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Enhancement-type MOSFET vs. Depletion-type
Enhancement
VDD gt 0
VDD lt 0
(NMOS)
(PMOS)
ID
VGS
VT lt 0
VGS gt 0
VGS lt 0
ID lt 0
ID gt 0
VGS
ID
VT gt 0
NMOS
PMOS
Depletion
(PMOS)
(NMOS)
VGS
VT gt 0
ID
ID
VGS
VT lt 0
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MOSFET I/V Relation
i) cutoff region VGS ltVT ID0
W
L
ii) nonsaturation(or triode) region
VGS?VT, OltVDS?VGS-VT
N
N
dV(x) dx
IDSW?nQn(x)
Gate
Drain
Source
Qn(x) of electrons per unit surface area ?n
electron mobility V(x) surface potential at x
QnCox(VGS -VT-VDS)
QnCox(VGS-VT)
Qn(X)qCOX(VGS-VT-V(X))
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Integrating both sides of
IDS
where
Material
process
Layout geometry
Short
Long-channel
Pinch-off point
IDS
(VGS-VT)
(VDS)
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IDS

• ii) Linear Region, VDS ? ?(0.1V)
• IDS?(VGS-VT)VDS analog multiplier
• iii) Saturation Region
• - MOSEF is called Square-Law Device
• - Remember ?q?nCoxW/L, where ?n ?

VGS
VDS
For VDS?VGS-VT indep. of VDS
(surface scattering)
Actually less than square
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Two causes for current saturation

• i) Pinch-off in long-channel device
• ii) Velocity saturation in short-channel device

v?E
v
v?E E ? Ecrit
vsat
vvsat E gt Ecrit
Ecrit
E
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5. Actual MOSFET(Secondary Effect)

• Threshold voltage variations
• i) Body effect(Substrate bias)
• ex.1 Series-connected MOSFETs
• - NMOSFET in 2-input NAND-gate
• - PMOSFET in 2-input NOR-gate
• VT of A-NMOS VT of
  A-PMOS depend on VY

VDD
VDD
X
A
Y
B
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ii) -DVT due to Short-Channel effect iii
) DVT due to Narrow-Channel effect(?)
VT
L(channel length)
(effective) charge per unit surface area
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iv) Drain-Induced Barrier Lowering(DIBL) for
small L ? can lead to Punch-through
ex. DRAM cell leakage current depends on the
voltage on the data line
VT
VDS
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Channel Length Modulation
LMASK
L
Xj
aXj
D L
VDS
LAMBDA(SPICE Level1 model parameter)
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Subthreshold Current

• Actually MOSFET is conducting also below VGS lt VT
  
• Subthreshold or weak inversion condition
• ID exp , Vth , 0 lt ? lt 1
• Reducing VT according to VDD down - scaling
  yields high subthreshold current.

ln ID
VGS
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Effect of Source, Drain Resistance
RD

-
VGS
Silicidation reduces polysilicon gate
resistance as well as RS, RD
RS
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Hot Electron Effect

• For submicron MOSFET, electron becomes hot due
  to strong E(electric field) ? 104 V/cm 1V/?m
• E is very high near the drain junction
• LDD(Lightly-Doped Drain) MOSFET is effective for
  reducing the E-field near drain junction.
• Hot electron captured in the gate oxide through
  tunneling causes VT instability(threshold drift).

n
n
n
n
n-
LDD-MOSFET
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CMOS Latchup

• i) When Rnwell Rpsubs 0
• latchup is impossible
• ii) When Rnwell Rpsubs ?
• ?n? ?p ? 1 causes latchup
• iii) When 0 lt Rnwell, Rpsubs lt ?
• ?n? ?p ? ? (? gt1) causes trouble

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6. CMOS Process

• Snapshot of IC fabrication process

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• Step 1 Crystal growing(Czochralskis
  method)
• 2 sawing
• 3 CMP(Chemical-Mechanical Polish)
• 4 SiO2-layer growth/Deposit(CVD) or
  Sputtering of poly, SiO2, Si3N4, Al
• 5 Resist Spin Coat
• 6 mask exposure
• 7 Resist develop
• 8 Oxide etch(using plasma/ion/wet)
• 9 Ion Implant for Impurity doping
• 10
• 11 Strip Resist
• 12 Strip Oxide

Repeated 12-20 times for a CMOS process
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Cross-section of MOSFET showing each
layerLOCOS(or Isoplanar) Process for PMOSFET
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MOSFET Formation Process

• 1. Field Implant
• 2. Grow Field Oxide
• Remove Nitride
• 3. Form Poly Gate deposit, dope, mask etch
• 4. Form Source/Drain for
• n-channel MOSFET
• n-type substrate contact
• 5. Form Source/Drain for P-channel MOSFET
  P-type substrate contact

Channel Stop


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Basic N-well CMOS Process
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Cross-section of CMOS Inverter in N-well CMOS
Process
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Substrate Well Contacts
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Twin-well CMOS
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CMOS Process Layers
Via 1
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Mask layer drawn

• N-well not(P-well) n-diffusion(silicon)
  CAA(mask)
• Active Pdiff ndiff ? CSN(mask) ?
• n-diffusion implant grow(ndiff) (?
  CPG(mask)
• P-diffusion implant grow(Pdiff)

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Sheet Resistance
R
process
layout geometry
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Reducing R with Silicide

• Silicide a metallic compound of silicon
• i) polycide reduces Rg
• ii) salicide reduces Rg, Rs and Rd

Metal (Ti,W,Ta,Co)
poly-Si
deposit, sinter etch
silicide
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Multi-Level Metalization issues

• Planarization of surface using CMP(Chemical-Mechan
  ical Polishing)

insulating glass
flat surface after grinding with slurry
rough surface
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• Inter-Level Interconnect
• I) diffusion contact/polysilicon contact using
  barrier metal(platinum)
• ii) contact plug or via plug Tungsten
• iii) sandwiched metal layer TiW/AlCu/TiW

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7. CMOS Layout Design Rules

• ?-based design rule all dimensions rep. as
  integer times ?, scalable.
• ex. Mead-Conway rule, MOSIS rev. 4-6
• ??m-based design rule some dimensions are not
  scalable.
• ex. Most company(foundry), MOSIS rev.7
• mixed(??) design rule
• 3 types of design rules
• FEOL(Front End of the Line)
• BEOL(Back End of the Line) metal interconnect
• Glass layer

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8. SPICE Model for MOSFET

• SPICE
• originally developed at Univ. Berkeley
• now many versions are available, e.g.,HSPICE,
  PSPICE, SmartSPICE, AIMSPICE,
• Models for R,L,C, VI source, diode, BJT, JFET,
  MOSFET, Transmission lines, MOSFETs, and
  Macros(Behavioral models), etc.
• Levels
• Level1(Schichman-Hodges Model) Simple, fast,
  good timing
• Level2(Grove-Frohman Model) Short, narrow
  channel effect, slow, convergence poor
• Level3(Empirical Model) Faster than Level2 while
  as accurate, convergence OK
• Level13(BSIM Model) Now most widely used
• Level27SOS Model

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• MOSFET is defined by
• MOSFET model element parameters,
• CAPOP model parameters gate capacitance
• ACM(Area Calculation Method) model parameters
  diode model
• Model selection
• each MOSFET is described by element .MODEL
  statement
• ex) M3 3 2 1 0 PCH .MODEL PCH PMOS LEVEL13
  ltparametersgt
• Analysis DC, transient, AC, and noise
• DC, transient analysis same except the inclusion
  of capacitances
• AC noise analysis replace Ids by gm, gds
  gmbs where gm , gds

DIds
DIds
DVgs
DVds
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Equivalent Circuit MOSFET Transient Analysis
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Equivalent Circuit, MOSFET AC Analysis
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MOSFET AC Noise Analysis
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LEVEL 13 BSIM Model

• Berkeley Short Channel IGFET Model(BSIM)
• VT VFB fB K1 fBVSB - K2(fBVSB) hVDS
• Sub-threshold current calculated when NO(ZNO) lt
  200

IlimIexp
IDS (weak-inversion current)
Ilim Iexp
IDS IDS,S IDS,w (continuous 1st
derivative bet. strong weak inversion
region)
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WREFeff

• Geometry-sensitivity Factors for Parameter
  Processing
• A A0 LA0 ( - )
  WA0 ( - )
• ex) VFB0 - 0.35(volt), LVFB0 -
  0.1(voltmicron), WVFB0 0.08(voltmicron)
  LREFeff 2 micron, WREFeff 10 micron
  zvfb VFB0 LVFB0 WVFB0
• Model parameters processed according to the
  device size start with z followed by the
  parameter name
• Bias-Sensitivity Factors( start with c )
• xu0 zu0 - zx2u0 vsb
• xu1 zu1 - zx2u1 vsb zx3u1 (vds - VDDM)

1
1
1
1
weff
Leff
LREFeff
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