Verilog-A:%20An%20Introduction%20for%20Compact%20Modelers

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Verilog-AAn Introductionfor Compact Modelers
MOS-AK/ESSDERC/ESSCIRC Workshop (Montreux 2006)

• Geoffrey Coram

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Outline

• The Problem
• Modeling Languages
• Diode Example
• Guidelines
• Admonishments
• Compiler Optimizations
• Conclusion
• References (and Further Examples)

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Many models, many simulators
Eldo
VBIC
ACM
Spectre
USIM
ADS
Smash
HiCUM
BSIM
HSIM
Mextram
Nanosim
APLAC
PSP
HiSIM
HSPICE
HVEKV
GoldenGate
AMS
MM20
from McAndrew, BMAS 2003
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The Solution
Eldo
VBIC
ACM
USIM
ADS
Smash
HiCUM
BSIM
HSIM
Modeling Interface
Mextram
Nanosim
APLAC
PSP
HiSIM
HSPICE
HVEKV
GoldenGate
AMS
MM20
from McAndrew, BMAS 2003
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Modeling Languages

• Programming languages
• FORTRAN (SPICE2)
• C (SPICE3)
• Fast, direct access to simulator
• Must compute derivatives
• No standard interface
• Intimate knowledge of simulator required
• MATLAB
• Excellent for data fitting
• Does not run directly in any analog simulator

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Behavioral Modeling Languages

• VHDL-AMS
• First analog behavioral modeling language working
  group (IEEE 1076.1)
• Painfully slow to come to fruition
• Europe prefers VHDL (for digital)
• Runs in
• AMS Designer (Cadence), DiscoveryAMS (Synopsys),
  ADVance MS (Mentor), Smash (Dolphin),
• only AMS simulators!
• No clear definition of VHDL-A (except by R.
  Shis MCAST model compiler)

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Behavioral Modeling Languages

• Verilog-A? Verilog-AMS
• Pushed by Cadence, came to market earlier
• Verilog-A from Open Verilog International became
  part of Accellera Verilog-AMS
• IEEE 1800 authorized to develop SystemVerilog-AMS
• Verilog-AMS runs in the same AMS simulators as
  VHDL-AMS
• Verilog-A runs in Spectre, HSpice, ADS,
  Eldoand internal simulators of semiconductor
  companies
• Clear definition of A
• Verilog-AMS LRM 2.2 was driven by the
  requirements for compact modeling

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V-AMS LRM 2.2 Additions

• Highlights for compact modeling
• output / operating point parameters
• vdsat, id_chan
• also gm, cgs using new ddx() operator
• simparam to access simulator quantities (gmin)
• param_given
• paramsets replace and extend Spice .model cards

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VHDL-AMS Diode

• -- Modified from http//www.syssim.ecs.soton.ac.uk
  /vhdl-ams/examples/smpr.htm
• library IEEE
• use IEEE.math_real.all
• use IEEE.electrical_systems.all
• use IEEE.FUNDAMENTAL_CONSTANTS.all
• entity diode is
• generic (Isat current 1.0e-14) --
  Saturation current Amps
• port (terminal p, n electrical)
• end entity diode
• architecture ideal of diode is
• quantity v across i through p to n
• constant TempC real 27.0 -- Ambient
  Temperature Degrees
• constant vt real PHYS_K(273.15 TempC
  )/PHYS_Q -- Thermal Voltage
• begin
• i Isat(limit_exp(v/vt) - 1.0)
• end architecture ideal

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VHDL-AMS Diode

• -- Modified from http//www.syssim.ecs.soton.ac.uk
  /vhdl-ams/examples/smpr.htm
• library IEEE
• use IEEE.math_real.all
• use IEEE.electrical_systems.all
• use IEEE.FUNDAMENTAL_CONSTANTS.all
• entity diode is
• generic (Isat current 1.0e-14) --
  Saturation current Amps
• port (terminal p, n electrical)
• end entity diode
• architecture ideal of diode is
• quantity v across i through p to n
• constant TempC real 27.0 -- Ambient
  Temperature Degrees
• constant vt real PHYS_K(273.15 TempC
  )/PHYS_Q -- Thermal Voltage
• begin
• i Isat(limit_exp(v/vt) - 1.0)
• end architecture ideal

is is a keyword!
TempC is a constant!
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Verilog-A Diode

• include "disciplines.vams"
• module diode(a,c)
• inout a,c electrical a,c
• parameter real is 10p from (0inf)
• real id
• (desc "conductance ") real gd
• analog begin
• id is (limexp(V(a,c) / vt) 1.0)
• gd ddx(id, V(a))
• I(a,c) lt id V(a,c)simparam("gmin",
  1e-12)
• end
• endmodule

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Verilog-A Diode

• include "disciplines.vams"
• module diode(a,c)
• inout a,c electrical a,c
• parameter real is 10p from (0inf)
• real id
• (desc "conductance ") real gd
• analog begin
• id is (limexp(V(a,c) / vt) 1.0)
• gd ddx(id, V(a))
• I(a,c) lt id V(a,c)simparam("gmin",
  1e-12)
• end
• endmodule

thermal voltage uses simulation temperature
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Verilog-A Diode
disciplines define through and across variables

• include "disciplines.vams"
• module diode(a,c)
• inout a,c electrical a,c
• parameter real is 10p from (0inf)
• real id
• (desc "conductance ") real gd
• analog begin
• id is (limexp(V(a,c) / vt) 1.0)
• gd ddx(id, V(a))
• I(a,c) lt id V(a,c)simparam("gmin",
  1e-12)
• end
• endmodule

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Verilog-A Diode

• include "disciplines.vams"
• module diode(a,c)
• inout a,c electrical a,c
• parameter real is 10p from (0inf)
• real id
• (desc "conductance ") real gd
• analog begin
• id is (limexp(V(a,c) / vt) 1.0)
• gd ddx(id, V(a))
• I(a,c) lt id V(a,c)simparam("gmin",
  1e-12)
• end
• endmodule

modules combine entity and architecturereplace
Spice primitives
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Verilog-A Diode

• include "disciplines.vams"
• module diode(a,c)
• inout a,c electrical a,c
• parameter real is 10p from (0inf)
• real id
• (desc "conductance ") real gd
• analog begin
• id is (limexp(V(a,c) / vt) 1.0)
• gd ddx(id, V(a))
• I(a,c) lt id V(a,c)simparam("gmin",
  1e-12)
• end
• endmodule

parameters have ranges (and defaults)
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Verilog-A Diode

• include "disciplines.vams"
• module diode(a,c)
• inout a,c electrical a,c
• parameter real is 10p from (0inf)
• real id
• (desc "conductance ") real gd
• analog begin
• id is (limexp(V(a,c) / vt) 1.0)
• gd ddx(id, V(a))
• I(a,c) lt id V(a,c)simparam("gmin",
  1e-12)
• end
• endmodule

built-in function with improved convergence
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Verilog-A Jump Start

• Looks much like C
• Intuitive and easy to read and learn
• Start with an existing model and modify
• Based on through and across variables
• Set up is for KCL and KVL
• Understand the contribution operatorI(di,si)
  lt Ids // current di to siV(d ,di) lt
  I(b_rd)rd // voltage d to di
• Dynamic flows are done via ddt() I(t,b) lt ddt(C
  V(t,b))

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Best Practices

• Models formulated in currents I(V) and charges
  Q(V)
• most natural for modified nodal analysis (MNA)
• Q(V) not C(V) to ensure conservation of charge
• ddt(Q(V)) ! ddt(C(V) V) ! C(V) ddt(V)
• No access to previous timesteps
• watch non-quasi-static formulations
• allows model to run in RF simulator
• Noises as current sources
• No discontinuities

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Discontinuities

• Spice requires continuous derivatives
• Consider this code
• if (vbs 0.0) begin
• qbs 0.0
• capbs czbsczbsswczbsswg
• end else if (vbs lt 0.0) begin
• qbs
• I(b,s) lt ddt(qbs)

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Discontinuities

• Resulting C code
• if (vbs 0.0)
• qbs 0.0
• dqbs_dvbs 0.0
• //capbsczbsczbsswczbsswg
• else if (vbs lt 0.0)
• qbs

Automatic derivative differs from intended value
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Discontinuities

• HiSIM2 Verilog-A(beta code)
• Clipping in C codemay affect values and
  derivativesdifferently

if ( Vds lt epsm10 ) begin Pds 0.0
Psl Ps0
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Compiler Optimizations

• Common subexpressions
• id is (exp(vd/vtm) 1.0)
• gd is/vtm exp(vd/vtm)
• Eliminating internal nodes
• if (rs 0.0)
• V(b_res) lt 0.0
• else
• I(b_res) lt V(b_res) / rs
• Dependency trees
• replace analysis() and initial_step

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analysis()

• Consider this code
• if (analysis("tran")) begin
• qd

• No capacitance in
• small-signal ac analysis,harmonic balance,
  envelope following
• Pseudo-transient homotopy

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analysis()

• Consider this code
• if (analysis("noise")) begin
• flicker strongInversionNoiseEval(vds, temp)

• But what about PNOISE, HBNoise, ?

• Compiler/Simulator MUST do this optimization

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Events

• Consider this code
• _at_(initial_step) begin isdrain jsat ad

• What happens for a dc sweep?
• dont want re-computing for bias sweep
• need re-computing for temperature sweep
• Even for transient, initial_step is true for
  every iteration at time0

• Compiler/Simulator MUST do this optimization

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ADMS Magic Names

• ADMS uses special block names to identify
  sections of code
• Eg PSP Verilog-A
• begin initializeModel
• NSUB0_i CLIP_LOW(NSUB0,1e20)
• //
• Doesnt hurt for other compilers

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Software Practices

• Use consistent indentation
• Align code vertically on
• Use meaningful names
• use maximum size (8) to help vertical alignment
• Include comments brief description, reference
  documentation
• Physical constants are not dated and could change
• model results would then change
• define physical constants for a model

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PSP Model Code

• // 4.2.4 Surface potential at source side
• Gf2 Gn2 f_s
• inv_Gf2 1.0 / Gf2
• Gf sqrt(Gf2)
• xi 1.0 Gf invSqrt2
• inv_xi 1.0 / xi
• Ux Vsbstar inv_phit1
• xn_s phib inv_phit1 Ux
• if (xn_s lt se)
• delta_ns exp(-xn_s) inv_f
• else
• delta_ns ke inv_f / P3(xn_s -
  se)
• margin 1e-5 xi
• sp_s(x_s, xg, xn_s, delta_ns)

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PSP Model Code

• // 4.2.4 Surface potential at source side
• Gf2 Gn2 f_s
• inv_Gf2 1.0 / Gf2
• Gf sqrt(Gf2)
• xi 1.0 Gf
• inv_xi 1.0 / xi
• Ux Vsbstar inv_phit1
• xn_s phib inv_phit1 Ux
• if (xn_s lt se)
• delta_ns exp(-xn_s) inv_f
• else
• delta_ns ke inv_f / P3(xn_s -
  se)
• margin 1e-5 xi
• sp_s(x_s, xg, xn_s, delta_ns)

equation number from documentation and
explanation
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PSP Model Code

• // 4.2.4 Surface potential at source side
• Gf2 Gn2 f_s
• inv_Gf2 1.0 / Gf2
• Gf sqrt(Gf2)
• xi 1.0 Gf invSqrt2
• inv_xi 1.0 / xi
• Ux Vsbstar inv_phit1
• xn_s phib inv_phit1 Ux
• if (xn_s lt se)
• delta_ns exp(-xn_s) inv_f
• else
• delta_ns ke inv_f / P3(xn_s -
  se)
• margin 1e-5 xi
• sp_s(x_s, xg, xn_s, delta_ns)

alignment for readability
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PSP Model Code

• // 4.2.4 Surface potential at source side
• Gf2 Gn2 f_s
• inv_Gf2 1.0 / Gf2
• Gf sqrt(Gf2)
• xi 1.0 Gf invSqrt2
• inv_xi 1.0 / xi
• Ux Vsbstar inv_phit1
• xn_s phib inv_phit1 Ux
• if (xn_s lt se)
• delta_ns exp(-xn_s) inv_f
• else
• delta_ns ke inv_f / P3(xn_s -
  se)
• margin 1e-5 xi
• sp_s(x_s, xg, xn_s, delta_ns)

indentationof blocks
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Other Model Code

• //----Self Heating Effect
• //(implemented only on mobility)------
• PD (VDE-VS)Id
• if (SH_switch 1) begin
• I(TH) lt PD
• RTHNOM RTHNOM_298K(1alpha_SHE(Tempp-TNOMK
  ))
• RTH RTHNOM(1alpha_SHE(TemppV(TH)-TNOMK))
  
• I(TH) lt - V(TH)/(RTH)
• I(TH) lt - ddt(CTHV(TH))
• end
• else begin
• I(TH) lt 0
• end
• Tratio_SH(TemppV(TH)SH_switch)/TNOMK
• BEXBEX0/pow( abs(VG-VS) 1e-1,par_SHE)
• KP_TKP0pow(Tratio_SH,BEX)

no reference to documentation
inconsistent indentation
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Other Model Code

• //----Self Heating Effect
• //(implemented only on mobility)------
• PD (VDE-VS)Id
• if (SH_switch 1) begin
• I(TH) lt PD
• RTHNOM RTHNOM_298K(1alpha_SHE(Tempp-TNOMK
  ))
• RTH RTHNOM(1alpha_SHE(TemppV(TH)-TNOM
  K))
• I(TH) lt - V(TH)/(RTH)
• I(TH) lt - ddt(CTHV(TH))
• end else begin
• I(TH) lt 0
• end
• Tratio_SH(TemppV(TH)SH_switch)/TNOMK
• BEXBEX0/pow( abs(VG-VS) 1e-1,par_SHE)
• KP_TKP0pow(Tratio_SH,BEX)

correct indentation
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Other Model Code

• // new model for mobility reduction,//linked to
  the charges model
• // !! mb 98/10/11 (r10) introduced
  fabs(Eeff) (jpm) //
• if ((qb eta_qiqi) gt 0.0) begin
• E0_Q_1 1.0 T0(qb eta_qiqi)
  end
• else begin
• E0_Q_1 1.0 - T0(qb eta_qiqi)
  end
• T0_GAMMA_1 1.0 T0GAMMA_sqrt_PHI
  // !! mb 97/06/02 ekv v2.6
• beta KP_Weff T0_GAMMA_1 / (Leq
  E0_Q_11e-60) // !! mb
  97/07/18

cryptic comments where is Eeff??
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Coding Style

• Verilog-A can be very readable
• Characterization engineers andsimulator people
  will read it
• Make a good impression!

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Conclusion

• Verilog-A is a powerful and easy-to-use compact
  modeling language
• Writing a good compact model still requires care
  and rigor
• Many examples now available

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References

• Designers Guide http//www.designers-guide.org/
  
• Forum
• Verilog-A model library (VBIC, MOS11, JFET, etc.)
• MCAST (Prof. CJ Richard Shi) http//www.ee.washing
  ton.edu/research/mscad/shi/mcast.html
• Automatic compiler beats hand-coded C

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Examples

• Verilog-A model library athttp//www.designers-gu
  ide.org/VerilogAMS/
• VBIC, MOS11, JFET, etc.
• Silvaco public domain models (non-commercial
  use)https//src.silvaco.com/ResourceCenter/en/
  downloads/verilogA.jsp
• BSIM3, BSIM4, BJT, etc.
• But watch out for _at_(initial_step)!
• PSP http//pspmodel.asu.edu/
• Mextram http//hitec.ewi.tudelft.nl/mug/
• HiCUM http//www.iee.et.tu-dresden.de/iee/
  eb/hic_new/hic_intro.html