Silicon on Insulator

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Silicon on Insulator

• Advanced Electronic Devices
• Karthik Swaminathan

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Reasons for SOI

• Replacement for SOS
• Need to extend Moores Law
• Commercial Availability of SOI wafers

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Advantages of SOI

• Reduced Source and Drain to Substrate
  Capacitance.
• Absence of Latchup.
• Lower Passive current.
• Denser Layout ? Low cost.

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SOI Wafer Fabrication

• Bond and Etch Back
• SIMOX (Separation by IMplantation Of oXygen)
• SIMON(Separation by IMplantation Of Nitrogen)

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SIMOX
SIMOX
silicon
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Fully Depleted (FD) SOI

• This is what you expect.
• FDSOI MOSFET
• Depleted channel.

http//www.soisic.com/SOI_keys_benefits.htm
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Partially Depleted (PD) SOI

• What if active Si layer is thick ?
• Body in channel floating ? Floating body effect.

http//www.soisic.com/SOI_keys_benefits.htm
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Is SOI just in the textbooks ?
1987 IBISs commercial SIMOX wafers (3 6)
1988 HPs 2GHz CMOS circuit
1989 TIs commercial 64k SRAM
March 2004 Apples Xserve G5
End 2004 AMD 90nm processor
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Novel SOI Devices

• Dual gate SOI.
• SOI Single electron transistors.

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Double-Gate SOI MOSFET

• ITRS roadmap dual gate SOI at 15nm.
• Thick gate oxide to ensure equal thickness on
  both sides.

IEEE Tran on Elec. Dev. 50,3,March
2003,Ultimately Thin Double-Gate SOI
MOSFETs Thomas Ernst et al.
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Issues Negative resist for EBL

• PMMA resist is a good positive resist for EBL.
• Do we have a good negative EBL resist ? high
  resolution.
• NO ? alternate techniques.

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Negative Resist SOI ?

• EBL.
• Plasma oxidation.
• Etching of amorphous silicon.
• BOX removal.

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Negative resist silicon ?

• EBL
• Plasma oxidation
• Electron cyclotron resonance chlorine etching of
  silicon.

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SOI SET
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TEM image of trenches
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AFM image of SET
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Conductance Oscillations Vds 10mV
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SET by pattern dependent oxidation
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Pattern dependent oxidation
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Pattern dependent oxidation

• Thermal gate oxidation.
• Oxygen diffuses through the BOX and reaches the
  pattern edges which are oxidized.
• Stresses due to volume change prevent oxidation
  of the island.

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Conductance Oscillations Ld50nm Vds 1mV
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Conductance Oscillations Ld70nm Vds 1mV
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Conductance Oscillations Ld100nm Vds 1mV
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Gate capacitance vs Ld
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Summary

• Future devices will involve SOI.
• SOI provides certain benefits over bulk CMOS for
  smaller gate lengths.
• SOI SETs may become a promising technology in the
  future.