Niagara

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Niagara

• A 32-way multithreaded SPARC processor
• Evert van Aart
• Cedric Nugteren

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Contents

• Information on our paper
• ILP versus TLP
• The Niagara architecture
• Paper evaluation
• Summary
• Questions

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Information on our paper (1/2)

• Niagara A 32-way multithreaded Sparc processor
• Published in IEEE Micro issue March-April 2005
• Written by Poonacha Kongetira, Kathirgamar
  Aingaran, Kunle Olukotun

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Information on our paper (2/2)

• Poonacha Kongetira is a director of engineering
  at Sun Microsystems
• Kathirgamar Aingaran is a senior staff engineer
  at Sun Microsystems
• Kunle Olukotun is an associate professor of
  electrical engineering and computer science at
  Stanford University

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ILP versus TLP (1/2)

• Instruction level parallelism (ILP)
• Thread level parallelism (TLP)
• Web services
• Databases

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ILP versus TLP (2/2)

• single-issue, single-thread pipeline
• single-issue, 2 threads, coarse-grain threading
• single-issue, 2 threads, fine-grain threading
• dual-issue, 2 threads, simultaneous threading
• and single-issue, 2 threads, chip multiprocessing

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The Niagara architecture (1/2)
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The Niagara architecture (2/2)
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Paper evaluation (1/2)

• Strong points
• Clear introduction to TLP
• Motivates the architecture
• Comprehensive overview of the architecture
• Weak point
• Biased

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Paper evaluation (2/2)

• The future
• Sun Niagara II
• 64 threads
• Sun Victoria Falls
• 128 threads
• More applications
• The web grows

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Summary
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Questions?