7-Segment Display

1
7-Segment Display

• DIO1 Board
• Verilog

2
Digilab2 DIO1 Boards
Four 7-segment displays
A0
A1
A2
A3
3
DIO1 Board Common Anodes
A0 A1 A2 A3
Pins
Pins
AtoG(60)
4
Multiplex displays
0
0
1
0
0 0 0 0 1 1 0
5
Multiplex displays
0
0
0
1
0 0 0 1 1 1 1
6
Multiplex displays
1
0
0
0
1 0 0 1 1 0 0
7
Multiplex displays
0
1
0
0
0 1 1 1 0 0 0
8
x7seg
9
x7seg.v
module x7seg(x,cclk,clr,AtoG,A) input
150 x input cclk, clr output 60
AtoG output 30 A reg 60 AtoG reg
30 A integer k reg 30 digit reg 10
count
10
// ctr2bit always _at_(posedge cclk or posedge
clr) if(clr) count lt 0 else count
lt count 1
11
// Mux4 always _at_(x,count)
case(count) 0 digit x1512 1
digit x118 2 digit x74 3
digit x30 default digit
x30 endcase
12
// seg7dec always _at_(digit)
case(digit) 0 AtoG 7'b0000001 1
AtoG 7'b1001111 2 AtoG 7'b0010010
3 AtoG 7'b0000110 4 AtoG
7'b1001100 5 AtoG 7'b0100100 6
AtoG 7'b0100000 7 AtoG 7'b0001111
8 AtoG 7'b0000000 9 AtoG
7'b0000100 'hA AtoG 7'b0001000 'hb
AtoG 7'b1100000 'hC AtoG 7'b0110001
'hd AtoG 7'b1000010 'hE AtoG
7'b0110000 'hF AtoG 7'b0111000
default AtoG 7'b0000001 // 0 endcase
13
// Acode always _at_(count) for(k 0 k lt 3
k k1) if(count k) Ak 1
else Ak 0 endmodule
Example count 10 A2 1 A0 A1 A3
0 A30 0100
14
x7seg_test.v
module x7seg_test(mclk,bn,led,ldg,SW,AtoG,A)
input 18 SW input mclk, bn output
ldg, led output 60 AtoG output
30 A wire 60 AtoG wire 30
A wire clr, cclk, bnbuf reg 230
clkdiv wire 70 fix
15
IBUFG U00 (.I (bn), .O (bnbuf)) assign
led bnbuf assign clr bnbuf
assign ldg 1 // enable 74HC373 latch
// Divide the master clock (50Mhz) always
_at_(posedge mclk) begin clkdiv lt clkdiv
1 end assign cclk clkdiv17 // 190
Hz assign fix 8'b10100101 x7seg U1(.x(fix,
SW),.cclk(cclk),.clr(clr),.AtoG(AtoG),.A(A)) en
dmodule