Review for Exam 2

1
Review for Exam 2
Using MUXs to implement logic Using ROMs to
implement logic Timing Analysis The internal
structure of flip-flops Flip-flop timings Rising
and falling edge triggered flip-flops Counters
and state machines Generating next state
equations from counter sequences. Implementation
using RS, D, T and JK flip-flops Reading state
sequence from timing diagrams Determining next
states from schematics Moore vs. Mealy Max
frequency for a state machine Verilog code
2
Implementing Logic Functions With Muxes

• Implement
• Z AB BC

I0 I1 I2 I3
4-to-1 MUX
Z
A B
3
Implementing Logic Functions With Muxes

• Implement
• Z AB BC

I0 I1 I2 I3
0
4-to-1 MUX
Z
A B
4
Implementing Logic Functions With Muxes

• Implement
• Z AB BC

I0 I1 I2 I3
0
1
4-to-1 MUX
Z
A B
5
Implementing Logic Functions With Muxes

• Implement
• Z AB BC

I0 I1 I2 I3
0
1
4-to-1 MUX
Z
0
C
A B
6
Implementing Logic Functions With Muxes
An alternate method
Z AB BC
Z 1 0 0 C 0
A0 B0 A0 B1 A1 B0 A1 B1
I0 I1 I2 I3
0
1
Z 1 1 1 C 1
4-to-1 MUX
Z
0
Z 0 0 0 C 0
C
Z 0 1 1 C C
A B
7
Using a ROM For Logic

• Specify a truth table for a ROM which implements
• F AB ABC
• G ABC C
• H ABC ABC ABC

8
Using a ROM For Logic

• Specify a truth table for a ROM which implements
• F AB ABC
• G ABC C
• H ABC ABC ABC

9
Using a ROM For Logic

• Specify a truth table for a ROM which implements
• F AB ABC
• G ABC C
• H ABC ABC ABC

10
Using a ROM For Logic

• Specify a truth table for a ROM which implements
• F AB ABC
• G ABC C
• H ABC ABC ABC

11
Timing Analysis
12
Timing Analysis
13
Timing Analysis
14
Timing Analysis
15
Timing Analysis
16
Timing Analysis
17
Timing Analysis
18
The internal structure of flip-flops
D-type Flip-Flop
19
The internal structure of flip-flops
T-type Flip-Flop
20
The internal structure of flip-flops
J
Q
Q
K
CLK
JK-type Flip-Flop
21
Flip-flop timingsClock-to-Q
D
Q
Q
CLK
tCLK ? Q tNOT tAND 2 x tNOR
22
Flip-flop timingsClock-to-Q
CLK
D
Q
tCLK ?Q
time
23
Flip-flop timingsSetup time
D
Q
Q
CLK
tsetup tNOT tAND 2 x tNOR
24
Flip-flop timingsSetup time
tsetup
CLK
D
Q
time
25
Flip-flop timingsHold time
D
Q
Q
thold tNOT
CLK
26
Flip-flop timingsHold time
thold tNOT
Clock edge
AND gate turns off, D can change
CLK
D
Q
time
27
Flip Flop Timing
thold
tsetup
CLK
D
Q
tCLK ?Q
time
28
Rising and falling edge triggered flip-flops
D
Q
Q
CLK
Falling Edge Triggered DFF
29
Rising Edge Triggered DFF
Rising and falling edge triggered flip-flops
D
Q
Q
CLK
30
Generating next state equations from counter
sequences.
Desired count sequence 00 01 00 10
11 00 If current state 00, next state
?????
Implemented count sequence 000 001 100
110 011 000
31
Implementation using RS, D, T and JK flip-flops
32
Reading state sequence from timing diagrams
WXYZ 0010, 0110, 0011, 0101, 1100, 1000, 1001,
1101, 1110, 0010
33
Determining next states from schematics
Q2
Q2 Q1 Q0 0 0 0 0 0 1
1 0 0 1 1 0
Q1
Q2
Q1
Initial state
Q0
CLK
Q1
Q2
CLK
Q2
Q0
Q0
Q1
Q0
CLK
34
Moore vs. Mealy
35
Max frequency for a state machine
Steps 1. Determine the delay through the Flip
Flops 2. Determine the delay through the IFL
(max) 3. Add in setup time 4. Determine the
smallest clock period possible 5. Max
frequency 1 -----------
------- clock period
36
Structural Verilog Code
and (output, input1, input2, ) nand (output,
input1, input2, ) or (output, input1, input2,
) nor (output, input1, input2, ) not
(output, input1) buf (output, input1) xor
(output, input1, input2, ) xnor (output,
input1, input2, )
37
Structural Verilog Code example
module mux21(q, sel, a, b) input sel, a,
b output q wire selbar, a1,
a2 not(selbar, sel) and(a1, selbar,
a) and(a2, sel, b) or(q, a1, a2) endmodule
38
Dataflow Verilog Code
39
Dataflow Verilog Code example
module mux21(q, sel, a, b) input sel, a,
b output q assign q (sel a) (sel
b) endmodule
OR
module mux21(q, sel, a, b) input sel, a,
b output q assign q sel?ba endmodule
40
Verilog Code Heirarchy
module mux41(q, sel, a, b, c, d) input10
sel input a, b, c, d output q wire tmp1,
tmp2 mux21 M0(tmp1, sel0, a, b) mux21
M1(tmp2, sel0, c, d) mux21 M2(q, sel1,
tmp1, tmp2) endmodule
a
b
c
d
mux41
sel
2
a
b
c
d
q
mux21
mux21
sel0
tmp1
tmp2
mux21
sel1
q