A 1-Tap 40-Gbps Decision Feedback Equalizer in a 0.18-mm SiGe BiCMOS Technology

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A 1-Tap 40-Gbps Decision Feedback Equalizer in a
0.18-mm SiGe BiCMOS Technology

• Adesh Garg, Anthony Chan Carusone and Sorin P.
  Voinigescu
• University of Toronto

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Motivation

• Electrical equalization has been found to be an
  effective way to mitigate PMD limited fibre
  optical channels
• Linear equalizer can be paired with a decision
  feedback equalizer (DFE) to further extend the
  transmission range and/or increase the data rates
• State of the art
• FFE demonstrated at speeds over 40-Gbps in
  silicon
• DFE demonstrated only recently at speeds up to
  10-Gbps in 0.13 mm CMOS as well as a 0.18 mm SiGe
  BiCMOS

Goal To design a 1-Tap DFE at 40-Gbps
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Architecture

• Look-ahead parallel computation of filter
• Advantages
• Parallelism employed to remove processing in
  feedback path
• Limits loading on summing node

• Direct Feedback filter processing in feedback
  path
• Disadvantages
• Multiple processing stages in feedback path
• Additional loading at summing node

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Architecture

• Implementation of the architecture requires
  considerable overhead within the clock
  distribution
• Clock path requires the highest bandwidth
• Difficult design
• Power intensive
• The retimers are replaced with slicers at the
  inputs of the selector to ease requirements on
  the clock distribution

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Circuit Description
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Circuit Description Broadband Front End

• Shunt-Series Input Buffer (TIA)
• Shunt feedback allows for broadband frequency
  response while matching to 50 W
• Resistive degeneration (Series feedback) employed
  to further improve input linearity
• Allows low noise bias without significantly
  limiting bandwidth

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Circuit Description Broadband Front End

• Threshold adjustment functionality
• Transition is strengthened with variable
  threshold
• Allows detection of missed bits

Input
Output
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Circuit Description Broadband Front End

• Threshold Adjustment Buffer
• High Speed Buffer
• linearity
• DC offset
• linear tuning with control voltage
• Adjust threshold up to 225mV

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Circuit Description Decision Selective Feedback
ECL Master Slave Flip flop
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Circuit Description Decision Selective Feedback
ECL Selector
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Circuit Description Decision Selective Feedback

• Design of critical path using sum of OCTC

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Circuit Description Decision Selective Feedback

• Design of critical path using sum of OCTC
• Minimize transistor time constants, by biasing at
  peak ft / fmax collector current density

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Circuit Description Decision Selective Feedback

• Design of critical path using sum of OCTC
• Minimize transistor time constants, by biasing at
  peak ft / fmax collector current density
• Minimize the interconnect capacitance to tail
  current ratio through layout and by increasing
  collector current

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Circuit Description Decision Selective Feedback

• Design of critical path using sum of OCTC
• Minimize transistor time constants, by biasing at
  peak ft / fmax collector current density
• Minimize the interconnect capacitance to tail
  current ratio through layout and by increasing
  collector current
• Minimize voltage swing (or load resistor)

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DIE Photo

1. Broadband front end
2. Slicers
3. Decision selective feedback
4. Output driver
5. Clock Buffer

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Measurements BERT20-ft SMA cable

• 20-ft SMA cable
• 16 dB of attenuation at 5GHz
• Measurement GoalHighest frequency BERT test
  possible at the University of Toronto

20-ft SMA cable S21
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Measurements BERT10-Gbps 20-ft SMA cable
Input Eye 20-ft SMA Cable
Equalized Output Eye
Jitterpp 10.22ps SNR 13.13 Rise time
18.7ps Vpp 290mV
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Measurements 40-Gbps LargeSignal Measurements
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Measurements 40-Gbps LargeSignal Measurements

• 9-ft SMA cable
• 17 dB of attenuation at 20GHz
• Measurement GoalProve error free functionality
  at 40-Gbps

9-ft SMA cable S21
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Measurements 40-Gbps LargeSignal Measurements
Input Eye 9-ft SMA Cable
Equalized Output Eye
Jitterpp 5.11ps SNR 9.1 Rise time 13.67ps
Vpp 320mV
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Measurements 40-Gbps LargeSignal Measurements

• Manually verified 508-bit sequence (4x27-1 PRBS)
  via the waveform capture feature of oscilloscope
• Errors in middle waveform indicated by arrows

Reference
DFE output a 0
DFE output a ? 0
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Measurement Summary
Technology Jazz Semiconductor 0.18 mm SiGe BiCMOS
Supply Voltage 3.3V
Data Rate 40-Gbps
Power Dissipation 760mW
Broadband front end 95mW
Slicers 160mW
Decision Selective Feedback 225mW
Output Driver 95mW
Clock Path 185mW
Return Loss lt -10 dB up to 40 GHz
Output Peak-to-Peak Jitter 5.11ps _at_ 40 Gbps
Rise/Fall time 13.67/6 ps _at_ 40 Gbps
Output Swing 324mV _at_ 40 Gbps
Chip Size 1.5mm2
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Conclusion

• Design
• 1-Tap look-ahead architecture
• Broadband up to 40-Gbps
• Broadband, linear, low noise input stage
• Performance
• Demonstrated equalization of a 20-ft SMA cable at
  10 Gbps
• BER of less than 10-12
• At 40-Gbps, the DFE equalized a 9-ft SMA cable
  with error free operation
• This is the first 40-Gbps DFE in silicon

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Acknowledgements

• NIT, OIT, CFI for test equipment
• NSERC, Gennum and Micronet for financial support
• Jazz Semiconductor for technology access
• CAD tools by the Canadian MicroelectronicsCorporta
  tion (CMC)

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Questions?
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Backup
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Fabrication

• Break out circuit of the broadband front end
• Linear measurements

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Measurements S-Parameter
Return Loss on High Frequency Ports
Broadband Front End S21
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Measurements Broadband Characterization
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Measurements Broadband Characterization
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Measurements BERT
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Measurements 40-Gbps LargeSignal Measurements