Asynchronous%20Circuit%20Verification%20and%20Synthesis%20with%20Petri%20Nets

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Asynchronous Circuit Verification and Synthesis
with Petri Nets
J. Cortadella Universitat Politècnica de
Catalunya, Barcelona
Thanks to Michael Kishinevsky (Intel
Corporation) Alex Kondratyev
(The University of Aizu)
Luciano Lavagno (Politecnico di Torino)
Enric Pastor (Universitat Politècnica de
Catalunya) Alex Taubin (The
University of Aizu) Alex
Yakovlev (University of Newcastle upon Tyne)
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Motivation

• Interfaces are often asynchronous
• Subsystems with different clocks often want to
  talk to each other
• Self timing provides functional and temporal
  modularity
• and no clock skew, low power,low EMI, average
  performance, ...

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Why Petri nets ?

• Formal model to specify causality, concurrency
  and choice between events
• Simple enough to easily derive state-level
  information (logic synthesis)
• Powerful enough to implicitly represent a large
  state space

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Outline

• Design flow
• Synthesis
• Specification
• State encoding
• Logic decomposition
• Synthesis of Petri nets
• Formal verification

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Design flow
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x
x
y
y
z
z
x-
z
x
y
z-
y-
Signal Transition Graph (STG)
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Synchronous
Asynchronous
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Next-state functions
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Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Design flow
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
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VME bus
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STG for the READ cycle
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
LDS
DSr
VME Bus Controller
LDTACK
DTACK
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Choice Read and Write cycles
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Choice Read and Write cycles
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Circuit synthesis

• Goal
• Derive a hazard-free circuitunder a given delay
  model andmode of operation

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Modes of operation

• Fundamental mode
• Single-input changes
• Multiple-input changes
• Input / Output mode
• Concurrencycircuit / environment

Currentstate
Nextstate
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STG for the READ cycle
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
LDS
DSr
VME Bus Controller
LDTACK
DTACK
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Speed independence

• Delay model
• Unbounded gate / environment delays
• Certain wire delays shorter than certain paths in
  the circuit
• Conditions for implementability
• Consistency
• Complete State Coding
• Output persistency

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Other synthesis approaches

• Burst-mode machines
• Mealy-like FSMs
• Fundamental mode (slow environment)
• VLSI programming
• Syntax-directed translation from
  CSP(Communicating Sequential Processes)
• No logic synthesis
• Circuit size Size of the specification

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Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Design flow
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
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State Graph (Read cycle)
DSr
DTACK-
LDS
LDTACK-
LDTACK-
LDTACK-
DSr
DTACK-
LDS-
LDS-
LDS-
LDTACK
DSr
DTACK-
D
D-
DSr-
DTACK
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Binary encoding of signals
DSr
DTACK-
LDS
LDTACK-
LDTACK-
LDTACK-
DSr
DTACK-
LDS-
LDS-
LDS-
LDTACK
DSr
DTACK-
D
D-
DSr-
DTACK
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Binary encoding of signals
DSr
DTACK-
10000
LDS
LDTACK-
LDTACK-
LDTACK-
DSr
DTACK-
10010
LDS-
LDS-
LDS-
LDTACK
DSr
DTACK-
10110
01110
10110
D
D-
DSr-
DTACK
(DSr , DTACK , LDTACK , LDS , D)
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Excitation / Quiescent Regions
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Next-state function
0 ? 1
0 ? 0
1 ? 1
1 ? 0
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Karnaugh map for LDS
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
1
1
1
-
-
-
-
-
0
0
0
0
0
0/1?
-
-
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Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Design flow
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
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Concurrency reduction
LDS
LDS-
LDS-
LDS-
10110
10110
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Concurrency reduction
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
(See todays presentation in this workshop for
more details)
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State encoding conflicts
LDS
LDTACK-
LDS-
LDTACK
10110
10110
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Signal Insertion
LDTACK-
LDS
LDS-
LDTACK
101101
101100
D-
DSr-
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Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Design flow
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
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Complex-gate implementation
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Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Design flow
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
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Hazards
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Hazards
1000
1100
1100
0100
0110
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Decomposition

• Global acknowledgement
• Generating candidates
• Hazard-free signal insertion
• Event insertion
• Signal insertion

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Global acknowledgement
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How about 2-input gates ?
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How about 2-input gates ?
c
z
b
a
a
y
b
d
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How about 2-input gates ?
0
c
0
z
b
a
a
y
b
d
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How about 2-input gates ?
c
z
b
a
a
y
b
d
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How about 2-input gates ?
c
z
y
d
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Strategy for correct logic decomposition

• Each decomposition defines a new internal signal
  of the circuit
• Method Insert new internal signals such that
• After resynthesis,some large gates are
  decomposed
• The new specification is hazard-free under
  unbounded gate delays

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Decomposition example
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y-
s
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s1
y-
s-
s-
s-
s
s0
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s1
y-
y-
1001
1011
s-
w
1001
z-
0011
1000
z-
w-
w
y
x-
1010
y
x
x-
0111
s
s0
z
z
0111
z- is delayed by the new transition s- !
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Signal insertion for function F
Insertion by input borders
State Graph
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Event insertion
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Properties to preserve
a is persistent
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Interactive design flow
Reachability analysis
Transformations Synthesis
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Theory of regions(Ehrenfeucht 90, Nielsen 92)
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Synthesis of Petri Nets
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Excitation closure
a
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Label splitting
a
d
b
a
d
b
b
d
c
c
d
b
c
d
b
b
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Formal verification

• Implementability properties
• Consistency, persistency, state coding
• Behavioral properties (safeness, liveness)
• Mutual exclusion, ack after req,
• Equivalence checking
• Circuit ? Specification
• Circuit lt Specification

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Property verification consistency
Specification
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Correctness environment ? circuit
Circuit
Failure circuit produces an event unexpected
(not enabled)by the environment
Environment
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Fighting the state explosion

• Symbolic methods (BDDs)
• Partial order reductions
• Petri net unfoldings
• Structural theory (invariants)

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Fighting with state explosion
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Representing Markings
p2 p3 p5 1
p0 p1 p4 p5 1
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Summary

• Asynchronous design is applicable to
• asynchronous interfaces
• high-performance computing
• low-power design
• low-emission design
• There is an increased interest of few, but large
  scale companies Intel, Philips, Sun, Sharp, ARM,
  HP, Cogency

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Summary (continued)

• Asynchronous circuits are more difficult to
  design than synchronous
• Formal models and CAD support are essential
• Petri nets have been one of the most successful
  formalisms for modeling asynchronous circuits
• Most steps of the design process covered by this
  tutorial are supported by the tool Petrify