Use%20of%20Partial%20Orders%20for%20Analysis%20and%20Synthesis%20of%20Asynchronous%20Circuits

1
Use of Partial Orders for Analysis and Synthesis
of Asynchronous Circuits

• Alex Yakovlev
• School of EECE
• University of Newcastle upon Tyne

Collaboration with A. Semenov,W. Vogler, A.
Kondratyev, V. Khomenko, M. Koutny, A.
Madalinski, I. Poliakov
2
Outline

• Motivation
• A bit of history
• Circuit models in Petri nets
• Properties to be checked
• Problems with unfolding models
• State Coding analysis
• Visualisation using unfoldings
• Deriving logic from unfoldings
• What next?

3
Motivation for asynchronous systems

• Asynchronous (self-timed) systems help
  variability-tolerant design and optimize
  power-performance tradeoff for nanometer
  technology
• Latest International Semiconductor Roadmap
  predicts 20 (40) of designs will be
  asynchronous, and by 2012 (2020)
• Active areas of asynchronous signalling and
  circuits low power and low EMI processing
  (automotive, smart-card), networks on chip, GALS

4
Motivation from circuit analysis

• Self-timed circuits can be highly concurrent,
  e.g. use of pipeline data flow structures, use of
  parallel branches in control of CPUs, concurrent
  resource allocation schemes (multi-way arbiters,
  switches etc.) state space can run into 1030
  for 100s of signals.
• Hence analysis and verification using explicit
  state space traversal is hard

5
Motivation from circuit synthesis

• In the synthesis domain, resolving state encoding
  problems and constructing next-state functions
  using state space models is limited to 30-40
  signals (relatively small controllers)
• Visualisation of state space is very hard, let
  alone examining groups of states about some
  properties

6
Circuit specification
7
State Graph
8
Modified Specification
9
The new State Graph
10
But how about this one?
11
A bit of history

• Early examples
• Flow chart, change chart methods by Gilles,
  Swartwout and Shelly late 50s, early 60s
• Signal Graphs for handshake control structures by
  Jump and Thiagarajan mid 70s
• Circuit synthesis from Taxograms by Starodoubtsev
  mid 80s
• Circuit analysis and synthesis using Change
  Diagrams and their unfoldings by Kishinevsky,
  Kondtayev, Taubin and Varshavsky late 80s.
• Relation-based approach to analysis of STG models
  by Rosenblum and Yakovlev late 80s

12
A bit of history

• Petri net unfolding prefix by McMillan (1992)
• Unfolding prefix for STGs and circuits by
  Kondratyev et al. and Semenov (1995)
• Unfolding-based analysis of Timed Circuits by
  Semenov and Yakovlev (1996)
• Unfolding-based synthesis using cover
  approximations by Semenov et al. (1997)
• Circuit analysis using contextual net unfoldings
  by Vogler et al. (1998)
• STG analysis using unfoldings and LP and SAT by
  Khomenko et al. (2002-2003)
• Circuit Synthesis from STG using unfoldings and
  SAT by Khomenko (2004)
• Visualization of STG-based Synthesis by
  unfoldings by Madalinski et al. (2003-2005)
• Combining decomposition and unfolding for
  STG-based Synthesis by Khomenko and Shaefer
  (2007)

13
Circuit models in Petri nets

• Event-based models Petri net transitions
  represent signal events
• Level-based models Petri net places model the
  values of signals

14
Logic Circuit Modelling
Event-driven elements
Petri net equivalents
C
Muller C-element
Toggle
15
Logic Circuit Modelling
Level-driven elements
Petri net equivalents
y(0)
x0
x(1)
y1
y0
x1
NOT gate
Read arcs
x0
x(1)
z(0)
z1
y0
y(1)
b
NAND gate
x1
z0
y1
16
Circuit Petri Nets
Level-driven elements
Petri net equivalents
Self-loops in ordinary P/T nets
y(0)
x0
x(1)
y1
y0
x1
NOT gate
x0
x(1)
z(0)
z1
y0
y(1)
b
NAND gate
x1
z0
y1
17
Logic Circuit Modelling examples
Pipeline data Stage

• Pipeline control must guarantee
• Handshake protocols between the stages
• Safe propagation of the previous datum before the
  next one

Data Out
Data In
Data Enable
Rin
Rout
Pipeline control Stage
Ain
Aout
18
Event-driven circuit
Non-speed-independence can be detected via
non-1-safeness check
19
Level-driven circuit
20
Level-driven circuit
Set-part
21
Level-driven circuit
Reset-part
22
Level-driven circuit
This sort of structures (acyclic Change Diagrams)
were built directly from logic eqns by
Kishinevsky et al. but only for distributive
circuits
23
Level-driven circuit
Without y2 in Set part of y1 this trace can
happen
I2
C1
C2
I2-
I1
C1-
C2-
I2
C1
disabling
24
Properties analysed

• Functional correctness (need to model
  environment)
• Deadlocks
• Hazards
• non-1-safeness for event-based
• non-persistency for level-based
• Timing constraints
• Absolute (need Timed Petri nets)
• Relative (compose with a PN model of order
  conditions)

25
Circuit Petri Nets
Level-driven elements
Petri net equivalents
Self-loops in ordinary P/T nets
y(0)
x0
x(1)
y1
y0
x1
NOT gate
x0
x(1)
z(0)
z1
y0
y(1)
b
NAND gate
x1
z0
y1
26
Unfolding Nets with Read Arcs
Unfolding with read arcs
PN with self-loops
Unfolding with self-loops
(work with W. Vogler, CONCUR 1998)
Combinatorial explosion due to splitting the
self-loops
Works nicely for read-persistent nets only
27
Petri Net mapping an example
corresponding Petri Net
source gate-level model
Multiple read arcs exiting one place bad for
unfolding!
Only one read arc per placeminimal impact on
unfolding
28
Unfolding and read arcs statistics
Test case Net size(places/ transitions) Without place splitting Without place splitting With place splitting With place splitting
Test case Net size(places/ transitions) N of events Unfolding time N of events Unfolding time
Counterflow stage controller 24/28 1541 36 ms 821 25 ms
SDFS ARISC 90/90 gt50000 gt1 min (halted) 164 18 ms
SDFS fork/join 112/132 gt50000 gt1 min (halted) 1055 134 ms
SDFS fork/join early prop. 112/134 gt50000 gt1 min (halted) 1790 277 ms
29
STG Unfolding

• Unfolding an interpreted Petri net, such as a
  Signal Transition Graph, requires keeping track
  of the interpretation each transition is a
  change of state of a signal, hence each marking
  is associated with a binary state
• The prefix of an STG must not only cover the
  STG in the Petri net (reachable markings) sense
  but must also be complete for analysing the
  implementability of the STG, namely consistency,
  output-persistency and Complete State Coding

30
STG Unfolding
STG
Binary-coded STG Reach. Graph (State Graph)
Uninterpreted PN Reachability Graph
STG unfold. prefix
p1
abcd
p1
p1(0000)
a
b
a
b
p2(1000)
p3(0100)
p2
p3
p2
p3
c
c
p4(0110)
p4(1010)
p4
c
c
d
d
p4
p4
p5(0111)
p5(1011)
p5
d
d
p5
p5
d-
d-
31
STG Unfolding
STG
Binary-coded STG Reach. Graph (State Graph)
Uninterpreted PN Reachability Graph
STG unfold. prefix
p1
abcd
p1
p1(0000)
a
b
a
b
p2(1000)
p3(0100)
p2
p3
p2
p3
c
c
p4(0110)
p4(1010)
p4
c
c
d
d
p4
p5(0111)
p5(1011)
p5
d
Not like that!
p5
d-
32
Consistency and Signal Deadlock
STG
PN Reach. Graph
STG State Graph
p1
ab
p1p6(00)
a
b
b
a
b-
p2p6(10)
p3p6(01)
p2
p3
a-
a-
b-
p1p4(00)
p1p4
b
a
b
a-
b-
a
b-
b
b
p1p5(01)
p2p4(10)
p2p4
p1p5
p3p4
p3p4(01)
p6
p4
b
b
b
b
b-
Signal deadlock wrt b (coding consistency
violation)
p2p5(11)
p2p5
p3p5
b
b-
b-
b-
b-
p5
33
Signal Deadlock and Autoconcurrency
p6
p1
STG State Graph
STG Prefix
ab
p1p6(00)
b
a
b
a
b-
p2p6(10)
p3p6(01)
p3
p2
a-
b-
a-
b-
p1p4(00)
b
p1
a
b
p4
p1p5(01)
p2p4(10)
p3p4(01)
b
b
p2
b
a
Signal deadlock wrt b (coding consistency
violation)
p2p5(11)
p5
b-
b-
p2
b-
Autoconcurrency wrt b
34
Verifying STG implementability

• Consistency by detecting signal deadlock via
  autoconcurrency between transitions labelled with
  the same signal (a a, where a is a or a-)
• Output persistency by detecting conflict
  relation between output signal transition a and
  another signal transition b
• Complete State Coding is less trivial requires
  special theory of binary covers on unfolding
  segments

35
Example VME Bus Controller
36
Example Encoding Conflict
37
Example Encoding Conflict
e10
e8
dtack-
dsr
e1
e2
e3
e4
e5
e6
e7
e12
lds
ldtack
dtack
dsr
lds
d-
dsr-
d
Code(conf)10110
Code(conf)10110
lds-
ldtack-
e9
e11
38
Detection of encoding conflicts using SAT solvers

• A special case of model checking!
• ? has the form CONF1?CONF2?VIOL
• VIOL is a constraint stating that the two
  configurations have the same final encodings and
  enable different sets of output signals

39
Beyond model checking

• Problem model checking just tells you whether
  some property holds, but its not enough for
  resolution of encoding conflicts and for deriving
  equations!

40
Example Resolving the conflict
dtack-
dsr
csc
001000
000000
100000
100001
lds
ldtack-
ldtack-
ldtack-
dtack-
dsr
011000
100101
010000
110000
ldtack
lds-
lds-
lds-
dtack-
dsr
110101
011100
110100
010100
d
d-
dtack
dsr-
csc-
011111
111111
110111
011110
41
Example Encoding Conflict
e10
e8
core
dtack-
dsr
e1
e2
e3
e4
e5
e6
e7
e12
lds
ldtack
dtack
dsr
lds
d-
dsr-
d
Code(conf)10110
Code(conf)10110
lds-
ldtack-
e9
e11
42
Example Resolving the conflict
43
Visualising conflicts Height map

• Cores often overlap
• Highest peaks are good candidates for signal
  insertion
• Analogy with topographic maps

44
Height map an example
Core map
Height map
45
Logic synthesis Next-state function

• The next-state function of each output or
  internal signal will be implemented as a logic
  gate in the circuit
• Defined for each such signal z at each reachable
  state M as
• Nxtz(M) Codez(M) ? Enabledz(M)
• The value is undefined (dont care) for
  unreachable states

46
Example Deriving equations
dtack-
dsr
csc
001000
000000
100000
100001
lds
ldtack-
ldtack-
ldtack-
dtack-
dsr
011000
100101
010000
110000
ldtack
lds-
lds-
lds-
dtack-
dsr
110101
011100
110100
010100
d
d-
dtack
dsr-
csc-
011111
111111
110111
011110
47
Example Deriving Equations
Code Nxtdtack Nxtlds Nxtd Nxtcsc
001000 000000 100000 100001 011000 010000 110000 100101 011100 010100 110100 110101 011110 011111 111111 110111 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 0 0 1 1
Eqn d d ? csc csc ? ldtack dsr? (?ldtack?csc)
48
Example Resulting Circuit
Data Transceiver
Device
Bus
d
lds
dtack
dsr
csc
ldtack
49
Logic synthesis on unfoldings

• Challenge how to do this without building the
  state graph, and using only the unfolding prefix?

50
Logic synthesis on unfoldings

• Problem given a prefix and a set X of signals
  which are known to be a support of the given
  output or internal signal z, compute the truth
  table of Nxtz
• Let ? CONF ? CODEX where CODEX relates the
  values of all signals in X with the configuration
• Compute the projection of ? onto X

Need to know how to compute projections!
51
Example computing projections

• a b c d e
• 0 1 0 0 1
• 0 1 0 1 0
• 0 1 0 1 1
• 0 1 1 0 0
• 0 1 1 0 1
• 0 1 1 1 0
• 0 1 1 1 1
• 1 0 0 0 1
• 1 0 0 1 0
• 1 0 0 1 1
• 1 0 1 0 0
• 1 0 1 0 1
• 1 0 1 1 0
• 1 0 1 1 1

• Proja,b,c ?
• a b c
• 0 1 0
• 0 1 1
• 1 0 0
• 1 0 1

52
Computing projections

• Proja,b,c ?
• a b c d e

Incremental SAT
UNSAT
53
Further developments

• Unfoldings for PNs with read arcs, beyond
  read-persistent nets
• Unfoldings for large circuit models (higher
  levels)
• Unfoldings of circuits with timing constraints
• Unfoldings for synthesis and re-synthesis driven
  by verification and optimization

54
Circuit Petri nets
The meaning of these numerous self-loop arcs is
however different from self-loops (which take a
token and put it back) These should be test or
read arcs (without consuming a token)
From the viewpoint of analysis we can disregard
this semantic discrepancy (it does not affect
reachability graph properties!) and use ordinary
PN unfolding prefix for analysis, BUT
55
Experimental results (from Semenov)
Example with inconsistent STG PUNT quickly
detects a signal deadlock on the fly while
Versify builds the state space and then detects
inconsistent state coding
56
General-purpose Petri Net mapping technique

• Signals are represented as elementary cycles
• Positive (negative) transitions of the cycles are
  built according to set (reset) logical function
• The logical functions are converted into DNF form
  and undergo boolean minimisation
• For each clause of the minimised DNF, a
  transition is added
• Transitions are connected to places corresponding
  to the literals of the DNF clause by means of
  read arcs

read arcs