System Design Challenges: Floorplanning

1
System Design Challenges Floorplanning Power
Planningin todays large chips

• Amin Farmahini Farahani
• Instructor Prof. S. Mehdi Fakhraie
• ASIC CMOS Course
• University of Tehran, School of ECE
• May 2006

This is a class presentation. All data are copy
righted to respective authors companies as
listed in the references and have been used here
for educational purpose only.
2
Outline

• Introduction
• FloorPlanning
• Power Planning
• Conclusion

3
Outline

• Introduction
• FloorPlanning
• Power Planning
• Conclusion

4
Introduction

• Technology allows us to build chips consisting of
  hundreds of millions of transistors.
• chips have several processors, large memories,
  peripherals, specific IP, and I/O.
• DSM forced us applying new attentions and
  methods.
• Design reusethe use of pre-designed and
  pre-verified coresis now the cornerstone of
  System Design (time to market).

Fig. From 7
5
Motivation

• Floorplanning power planning helps avoid IR
  drop and electromigration problems.
• The complexity of todays designs have forced
  physical planning earlier in the flow.

6
Definitions

• Macro (IP, Child Block)
• design unit that can reasonably be viewed as a
  stand-alone subcomponent of a complete design.
• Subblock
• a subcomponent of a macro (too small or specific
  to be a stand-alone design component).
• Soft macro
• one that is delivered as synthesizable RTL code.
• Hard macro
• one that is delivered as a GDSII file. It is
  fully designed, placed, and routed by the
  supplier (layout level).

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Standard-cell vs. Mixed-mode

• Motivation IP reuse

Different blocks designed by different companies
Fig. From 6
8
Outline

• Introduction
• FloorPlanning
• Power Planning
• Conclusion

9
Hard Macro Placement

• Poor quality hard macro placement ? failure in
  area, freq.
• As the number of logic gates and hard macro
  instances increases, placement becomes
  challenging (combination of hard macro and
  standard cells).
• hundred hard macro instances with different sizes
  and shapes.

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Hard Macro Placement (cont.)

• Some hard macros must be placed next to specific
  IO cells such as PLLs, DAC to allow wide
  connections.
• normal method pre-place and fix these macros
  in specific locations (typically side bar)
• Blockages for the rest of the design.
• rectilinear core area for the rest of the design.
• Routing bottlenecks.
• Long routes for some macros.

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Simultaneous Std. Cell Macro Placement

• Normal method do not result in optimized
  placement because both macros and standard cells
  are not considered simultaneously during
  wire-length optimization.
• Normal method ensures maximal contiguous
  (minimally fragmented) space for std. cells, but
  may result in long routes.
• So we need a better algorithm consider both std.
  cells and macros simultaneously.
• Tradeoff between standard cell space
  fragmentation and wire-length is necessary.

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Two Placement

• Standard cells surrounded by hard macros are
  unroutable designs can be optimized to improve
  routablility by placement algorithms that do not
  create these types of areas 2.

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Automated Grouping
Fig. From 2

• Automated placement results (JupiterXTTM)

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Pins Position

• Std. cells usually are approximated with all the
  pins at the center.
• length of a net is Manhattan distance between
  their centers.
• For larger macros, approximating the pins at the
  center introduces significant inaccuracies.
• Using the actual pin locations makes the
  optimization process more difficult.
• Also consider orientation problems.

15
Outline

• Introduction
• FloorPlanning
• Power Planning
• Conclusion

16
Power Planning

• Creation of the power network within a design
• Power planning is integrated with the overall
  design flow and must be taken into account early
  in the design process because
• of pads may determine physical size (pad
  limited).
• The power structures within the core area consume
  physical area.
• The power grid topology effects top level
  routability, and also placement and routing
  within the child blocks.
• The power structure effects functionality and
  reliability.

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Simplified Power Distribution Architecture (four
basic elements)
Fig. From 3
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Power Network Elements

• Power Pad
• Power Rings
• Form complete rings around the periphery of the
  die, around individual hard macros, or inside of
  hierarchical blocks.
• higher-level Metal layers
• Power Straps/Trunks
• Horizontal (strap) and vertical (trunk) metal
  wires placed in an array across the entire or
  section die.
• higher level routing layers
• typically uniformly distributed across the die.
• Power Rails
• Is used to connect the standard cell power rails
  together, and or power trunks.
• Low level, typically metal 1.

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Power Rings

• Floorplanning tool insert rings respecting
  available space in IO area.
• User specify width and spacing of the rings.
• rule of thumb each side of the ring must carry a
  quarter of the current. divide overall power
  budget by four, using voltage, and current
  density for the metal layer determine the
  required width.
• It is best to create power and ground rings
  around any hard macro IP present in the design.

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Power and Ground Trunks

• Standard cell power rails are usually determined
  by the standard cell technology being used.
• Power rings and standard cell power rails have
  very little flexibility.
• straps and trunks have the most control and
  flexibility.
• Most important means to address detailed IR drop
  across the power network.
• A balance must be established between the need to
  retain routing resource for signal routes and the
  need to minimize IR drop.

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System Level Signal Integrity (SI)

• Timing Failures crosstalk between nets can
  change the delays.
• Functional Failures noise coupling between nets
  and/or cells can induce glitches.

Fig. From 3
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Signal Integrity

• Resolution eliminate long parallel routes near
  the edge and at the top metal layer of a child
  block.
• Method wiring keepout halo, partially around
  child block and partially at the top level.
• place buffers inside of the block close to the
  ports of the block. Thus, for top level signals
  the amount of wire that exists inside of the
  block is minimized.

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Outline

• Introduction
• FloorPlanning
• Power Planning
• Conclusion

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Conclusion

• Reuse attitude is required.
• Reuse permits complex designs.
• Well designed re-usable IP components enable
  successful design.
• Starting power integrity and floorplanning early
  is highly worthwhile in huge designs, because it
  avoids many problems in the later stages of the
  design flow.

25
References

• M. Keating, and P. Bricaud, Reuse Methodology
  Manual for System-On-A-Chip Designs, 3rd Ed.,
  Kluwer Academic.
• N. Kaul, and S. Kister, Hard Macro Placement in
  Complex SoC Design, Synopsys Inc., Sep. 2004,
  Available www.SoCcentral.com.
• R. Rodgers, K. Knapp, and C. Smith,
  Floorplanning Principles, SNUG (Synopsys User
  Group Conference), San Jose, 2005, Available
  www.synopsys.com.
• H. Piroozi, and K. Gopinathannair, A
  Hierarchical Rail Analysis Flow for Multimillion
  Gate SoCs Challenges and Solutions, SNUG
  (Synopsys User Group Conference), San Jose, 2005,
  Available www.synopsys.com.
• D. Stringfellow, and K. Knapp, Power Integrity
  for SoCs Power Planning and Signoff Flows,
  Synopsys Inc., Nov. 2005, Available
  www.synopsys.com.
• S. Adya, and I. Markov, Combinatorial techniques
  for mixed mode placement, University of
  Michigan, Available www.eecs.umich.edu/imarkov/E
  ECS527-Win03.
• JupiterIO Concurrent Die/Package IO Planning,
  Synopsys Inc., 2005.
• S. Idgunji, S. Lloyd, R. Mitchell, R. Spillman,
  and J. Young, Design Planning Strategies to
  Improve Physical Design FlowsFloorplanning and
  Power Planning, Synopsys Inc., Aug. 2003,
  Available www.synopsys.com.
• L. L. Azuara, and R. Dorsch, Design for Reuse in
  embedded system design, Available
  www.iti.uni-stuttgart.de/rainer/Lehre/SOCfCA01/Pr
  esentation9.

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Thanks

• Thanks for putting up with all my talk
• ?Any Question?