Functional Test Generation Based on Constraint Logic Programming

1
Functional Test GenerationBased on Constraint
Logic Programming

• Kesava Reddy Talupuru
• March, 2003
• Dept. of Elec. Comp. Engineering, University of
  Massachusetts, Amherst

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Outline

• Introduction
• Symbolic simulations
• Previous SAT approaches
• Constraint Logic Programming
• Implementation in ILOG Solver
• Manual Results

3
Existing Approaches to Design Validation and
Verification
Behavioral HDL
Simulation
Model Checking
Simulation
Theorem Proving
Seq. Equiv. Check.
Structural RTL
Specification w/ Properties
Equiv. Check.
S.T.E
Gate-level or Switch-level
4
Existing Approaches to Design Validation and
Verification
Specification w/ Properties
Simulation
S.T.E
Model Checking
Theorem Proving
Gate-level or Switch-level
Behavioral HDL
Structural RTL
Simulation
Equiv. Check.
Seq. Equiv. Check.
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Simulation for Design Validation

• Methodologies used to generate stimulus
• Directed testing
• Manual - time-consuming
• Random testing
• Weighted pseudo-random
• Constrained pseudo-random
• Deterministic Functional Test Generation
• Based on Satisfiability (SAT) and/or algorithms
  of Automatic Test Pattern Generation (ATPG)
• Requires coverage metrics

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Simulation forDesign Validation
100
80
60
Functional Coverage
Test Development Time
7
Where Functional Test Generation Can Help?

• Testing Corner cases
• Improve functional coverage in simulation
• Falsify a model by generating a counter example
• Cannot be used to prove a model is correct

8
The Validation Framework using Functional Test
Generation
Test Bench
Coverage Metrics
HDL
Coverage goal met?
Y
Directed/Random Simulation
Done
N
Pick a missed target, Simulate to seed environment
Abort
Sat?
Y
N
Symbolic Simulation
Formulate as a SAT problem
SAT Search
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Symbolic Simulation
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Symbolic Simulation (contd)

• Features
• Generates non-canonical expressions
• Starts at seed environments
• Fixed of time frames
• To further reduce complexity
• Cone-of-influence
• Tying inputs to constants

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Formulating a SAT Problem

• Specify the target and generate symbolic
  expressions
• Specify value requirements at different time
  frames
• Specify the constraints present on the inputs, if
  any

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Formulating a SAT Problem -Example
Symbolic Eq.
if (s 1) F E else F D
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Formulating a SAT Problem -Example
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Specify Requirement
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Finite State Machine Control for the data path of
MIPS processor
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Verilog Test bench
module mips_controller() reg 310 IR integer
list_h1, list_h2, profile_h integer
group_h, seed wire 30 states reg
clk, reset Controller I0 ( clk, rst, IR, .
states) initial begin tb_list_create(list_h1,
list_h2) tb_list_append_values ( list_h1, LW,
SW, Add ) random_h tb_random(seed, list_h,
IR) group_h tb_group(random_h)

(Contd).
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Verilog Test bench (contd)
tb_profile_create ( profile_h,
states) tb_update (group_h) tb_monitor_profile
(profile_h) tb_update_profile (profile_h)
_at_(posedge clk) tb_update (group_h) .. Continue
random simulation for a while.After some time
start symbolic sim.. symbolic_trace ( number of
clock cycles you want to trace ) tb_update
(group_h) tb_monitor_profile (profile_h) sat
_name( blif file) eqlist_strace(states) end
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Results of the design simulation
Profile monitor States (4h0) 1
20.00 (4h1) 0 0.00 (4h2) 2
15.00 . (4hf) 4
33.00 endprofile
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Block Diagram Representation of the previous
Verilog Test bench

Constrained random transaction generator
Design Model Under Test
Functional Coverage Monitor
Result Checker
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Previous Work to SAT

• Boolean Methods
• CNF-Based SAT (DPLL62)
• Conflict Driven
• Efficient Engineering
• Gate-level ATPG
• Circuit structure information
• BDD-based SAT
• CNF-based Gate-level circuit information

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Previous Work to Word-Level SAT

• Hybrid approaches
• CNF-Based SAT and linear programming relaxation
  Fallah98
• Word-level ATPG and modular arithmetic solver
  Huang00
• Summary Arithmetic constraints and Boolean
  constraints are solved using different solution
  framework
• Drawbacks
• Constraint propagation across the boundary not
  systematic
• Conflict-based learning across the boundary
  difficult to diagnose the reason and record the
  learning

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Previous Work to Word-Level SAT

• Unified Approach (Linear Programming SAT (LPSAT)
  )
• Preserve word-level operators
• Models arithmetic operators and Boolean logic in
  a unified domain
• Constraint propagation is implicit to one engine
• More systematic and efficient than a hybrid
  approach
• The state-of-the-art generic constraint solving
  techniques are applied

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Motivation

• LPSAT
• Supports only linear constraints ( Non-linear
  constraints should be transformed to linear)
• Numerical convergence problem
• Caused by big coefficients in linear constraints.
  
• A B 1073741824 s lt
  1073741823
• A B 1073741824 s gt 0
• Optimization Oriented, but the problems are of
  SAT nature
• To overcome above limitations, Constraint Logic
  Programming is proposed with ILOG Solver as
  constraint solving engine

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Constraint Logic Programming SAT (CLP-SAT)

• CLP logic programming with capability of
  constraint solving
• Constraint Programming Representation of a
  problem in terms of
• Its unknowns i.e. its variables,
• constraints that must be satisfied by these
  variables

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Constraint Satisfaction Problem (CSP)

• A CSP consists of
• a set of variables
• for each variable, a finite set of possible
  values (its domain)
• set of constraints restricting the values that
  the variables can simultaneously take
• A solution to a CSP is
• An assignment of a value from its domain to every
  variable
• Such a way that every constraint is satisfied

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Different kinds of Solutions

• Just one solution, with no preference as to which
  one
• All solutions
• An optimal, or at least a good solution, given
  some objective function defined in terms of some
  or all of the variables

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Advantages of Constraint Programming

• The representation is often much closer to the
  original problem
• the variables of the CSP directly corresponds to
  problem entities, and
• the constraints can be expressed without having
  to be translated into linear inequalities
• Choice of good heuristics to guide the solution
  strategy
• Different Constraint programming tools are
  available to express and solve constraints (ILOG
  solver, CHIP)

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Constraint Propagation

• Propagation is done by checking consistency
• Arc Consistency
• Path Consistency
• Def. Arc Consistency
• If there is a binary constraint Cij between
  the variables xi and xj then the arc (xi , xj) is
  arc consistent if for every value of a Di,
  there is a value b Dj such that the
  assignments xi a and xj b satisfy the
  constraint Cij.

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Example of Arc Consistency
Making (x, y) Arc consistent
domain reduced
domain reduced
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Basic Search Algorithms

• Backtracking Algorithm
• Organize the search in the form of decision tree
• Each node corresponds to a decision
• Build a feasible solution incrementally
• Stop and backtrack as soon as the current partial
  solution cannot lead to a feasible solution
• Check for consistency between the present and
  past variables

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Backtracking Sequence
dead end
?
dead end
dead end
?
start
?
?
dead end
dead end
?
success!
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Forward Checking Algorithm

• Check the constraints between the current (past)
  variables and future variables
• Assign a value to the current variable
• Remove the values (temporarily) from the domain
  of the future variable that conflicts with the
  current assignment
• If the domain of future variable becomes empty,
  then the current partial solution is inconsistent
  and backtrack to the previous point

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Introduction to ILOG solver

• Commercial tool for modeling and solving
  constraints
• Implemented in C
• Uses backtracking, forward checking algorithms,
  etc. internally for solving constraints

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Functioning of ILOG system
Decision making new constraints backtracking
Search
Problem specificat-ion
Variables, Domains and Constraints
Problem definition
Partial solution
Initial variables, constraints and domains
Constraint Propagation
Reduce domains, deduce constraints,contradictions
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Example
Search
Problem specificat-ion
x in 13, y in 1..3, z in 1..3 Constraints
x-y 1 y lt z
x in 13, y in 1..3, z in 1..3 Constraints
x-y 1 y lt z
Partial solution
Initial variables, constraints and domains
Constraint Propagation
Reduce domains, deduce constraints,contradictions
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Example
Search
Problem specificat-ion
x in 13, y in 1..3, z in 1..3 Constraints
x-y 1 y lt z
Initial variables, constraints and domains
Reduce domains, deduce constraints,contradictions
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Example
Search
Problem specificat-ion
12
23
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x in 13, y in 1..3, z in 1..3 Constraints
x-y 1 y lt z
Initial variables, constraints and domains
Reduce domains, deduce constraints,contradictions
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Example
Search
y 2
new constraints
Problem specificat-ion
12
23
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x in 13, y in 1..3, z in 1..3 Constraints
x-y 1 y lt z
Initial variables, constraints and domains
Reduce domains, deduce constraints,contradictions
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Example
Search
y 2
new constraints
Solution found!! Done
Initial variables, constraints and domains
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Implementation Issues
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Design Examples
A SAT instance can be either in Boolean or
Multi-Valued Network
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Word-level SAT Flow
A SAT Instance
Network Partitioning
Boolean
Arithmetic
Simplification
Model Boolean
Model Arithmetic
Combined w/ Value Requirements Relation
Constraints
Constraint Solving Engine
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Modeling Operators / Logic Gates in ILOG
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Example of Modeling a design in ILOG
int main() IloEnv env IloModel
model(env) IloIntVar A (env, 0, 3) model.add (F
A B) model.add (E B C) model.add
(HE D) model.add (G F gt E) model.add (s
A B) model.add (IloIfThen(s 0), (Z
G)) model.add (IloIfThen(s 1), (Z
H)) IloSolver solver(model)
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How to implement Mux ?
Select signals more than one
Cannot use IloIfThen()
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Overall Flow of the Functional Verification using
ILOG solver