EECE579: Digital Design Flows

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EECE579 Digital Design Flows

• Usman Ahmed
• Dept. of ECE
• University of British Columbia

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Implementing Digital Circuits
Digital Circuit Implementation Approaches
Custom
Semicustom
Cell-based
Array-based
Standard Cells
Gate Arrays Structured ASICs
FPGA's
Macro Cells
Compiled Cells
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Implementing Logic Circuits

• Design Iteration

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Standard Cell Design

• Library of cells that implement different
  gates
• Cells can have different width but all cells have
  same height
• (hence Standard Cells)
• Many variants of the same cell

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Standard Cell Design

• Logic Synthesis
• Transform the HDL description into library cells
• Placement
• Where to place a cell ?
• Routing
• Connect the placed cells.

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Standard Cell Design

• Optimizations
• Gate Resizing
• Buffer Insertion
• In-place Re-synthesis

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Standard Cell Design An Example
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Standard Cell Design

• Routing channel can be narrowed if more
  interconnect layers are available

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Standard Cell Design New Generation

• Cell-structure hidden under interconnect layers

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Standard Cell Design Summary

• Used only for the high-speed or low-power
  applications
• Very expensive, and time consuming
• (gt 2M just for the mask costs)
• Very high re-spin cost

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FPGAs

• FPGA Field-Programmable Gate Array

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Whats Inside an FPGA?

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Whats Inside an FPGA?

I/O Blocks - interface off-chip - can usually
support many I/O Standards
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Whats Inside an FPGA?

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Logic Block
Basic Logic Gate Lookup-Table Function
of each lookup table can be configured by
shifting in bit-stream.

Inputs
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Logic Clusters
Several lookup tables are grouped into
clusters - Typically 8 to 10 lookup
tables per cluster Connections between lookup
tables in the same cluster are fast Connections
between lookup tables in different clusters are
slow

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Whats Inside an FPGA?

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Reconfigurable Logic
Connect Logic Blocks using Fixed Metal Tracks and
Programmable Switches
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Reconfigurable Logic
Connect Logic Blocks using Fixed Metal Tracks and
Programmable Switches
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Implementing Systems in an FPGA
FPGA Fabric
Embedded memories
Embedded PowerPC
Hardwired multipliers
Xilinx Vertex-II Pro
High-speed I/O
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• Advantages of FPGAs
• "Instant Manufacturability" reduces time to
  market
• Cheaper for small volumes because you dont need
  to pay for fabrication
• means you dont need to be a big company to make
  a chip
• Relaxes Designers -gt relaxed designers live
  longer!
• Disadvantages of FPGAs
• Slower than custom or standard cell based chips
• Cannot get as much circuitry on a single chip
• Today 1M gates is the best you can do
• 200 MHz is about as fast as you
  can get
• For large volumes, it can be more expensive than
  gate arrays and custom chips

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Structured ASICs

• Combines good features of FPGAs and Standard Cell
  ASICs

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Logic Blocks

• Choices
• Fine Grained
• Basic gates NAND, NOR, XOR, FF etc.
• Medium Grained
• Lookup Tables
• Coarse Grained
• Multi-input, Multi-output blocks (e.g., PLAs)
• Configurability
• SRAM cells
• Vias
• Lower Level (e.g., between M1 and M2)
• Upper Level (Via stacks brought up to the
  configurable layers)

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Routing Fabrics

• Metal and Via Programmable
• More flexibility, more efficiency
• Employed in most structured ASIC offerings
• Via Programmable
• Regular, easy to manufacture
• Metal is fixed and every segment may not be fully
  utilizable,
• ? Can be Inefficient

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Design Flows
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Design Flows
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Design Flows
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Design Flows
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Design Flows
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Implementing Logic Circuits

• Design Iteration